1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Sysam stmark2 board configuration 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * (C) Copyright 2017 Angelo Dureghello <angelo@sysam.it> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __STMARK2_CONFIG_H 10*4882a593Smuzhiyun #define __STMARK2_CONFIG_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define CONFIG_STMARK2 13*4882a593Smuzhiyun #define CONFIG_HOSTNAME stmark2 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define CONFIG_MCFUART 16*4882a593Smuzhiyun #define CONFIG_SYS_UART_PORT 0 17*4882a593Smuzhiyun #define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define LDS_BOARD_TEXT \ 20*4882a593Smuzhiyun board/sysam/stmark2/sbf_dram_init.o (.text*) 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define CONFIG_TIMESTAMP 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define CONFIG_BOOTARGS \ 25*4882a593Smuzhiyun "console=ttyS0,115200 root=/dev/ram0 rw " \ 26*4882a593Smuzhiyun "rootfstype=ramfs " \ 27*4882a593Smuzhiyun "rdinit=/bin/init " \ 28*4882a593Smuzhiyun "devtmpfs.mount=1" 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define CONFIG_BOOTCOMMAND \ 31*4882a593Smuzhiyun "sf probe 0:1 50000000; " \ 32*4882a593Smuzhiyun "sf read ${loadaddr} 0x100000 ${kern_size}; " \ 33*4882a593Smuzhiyun "bootm ${loadaddr}" 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define CONFIG_EXTRA_ENV_SETTINGS \ 36*4882a593Smuzhiyun "kern_size=0x700000\0" \ 37*4882a593Smuzhiyun "loadaddr=0x40001000\0" \ 38*4882a593Smuzhiyun "-(rootfs)\0" \ 39*4882a593Smuzhiyun "update_uboot=loady ${loadaddr}; " \ 40*4882a593Smuzhiyun "sf probe 0:1 50000000; " \ 41*4882a593Smuzhiyun "sf erase 0 0x80000; " \ 42*4882a593Smuzhiyun "sf write ${loadaddr} 0 ${filesize}\0" \ 43*4882a593Smuzhiyun "update_kernel=loady ${loadaddr}; " \ 44*4882a593Smuzhiyun "setenv kern_size ${filesize}; saveenv; " \ 45*4882a593Smuzhiyun "sf probe 0:1 50000000; " \ 46*4882a593Smuzhiyun "sf erase 0x100000 0x700000; " \ 47*4882a593Smuzhiyun "sf write ${loadaddr} 0x100000 ${filesize}\0" \ 48*4882a593Smuzhiyun "update_rootfs=loady ${loadaddr}; " \ 49*4882a593Smuzhiyun "sf probe 0:1 50000000; " \ 50*4882a593Smuzhiyun "sf erase 0x00800000 0x100000; " \ 51*4882a593Smuzhiyun "sf write ${loadaddr} 0x00800000 ${filesize}\0" \ 52*4882a593Smuzhiyun "" 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* Realtime clock */ 55*4882a593Smuzhiyun #undef CONFIG_MCFRTC 56*4882a593Smuzhiyun #define CONFIG_RTC_MCFRRTC 57*4882a593Smuzhiyun #define CONFIG_SYS_MCFRRTC_BASE 0xFC0A8000 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* spi not partitions */ 60*4882a593Smuzhiyun #define CONFIG_JFFS2_CMDLINE 61*4882a593Smuzhiyun #define CONFIG_JFFS2_DEV "nor0" 62*4882a593Smuzhiyun #define MTDIDS_DEFAULT "nor0=spi-flash.0" 63*4882a593Smuzhiyun #define MTDPARTS_DEFAULT \ 64*4882a593Smuzhiyun "mtdparts=spi-flash.0:" \ 65*4882a593Smuzhiyun "1m(u-boot)," \ 66*4882a593Smuzhiyun "7m(kernel)," \ 67*4882a593Smuzhiyun "-(rootfs)" 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun /* Timer */ 70*4882a593Smuzhiyun #define CONFIG_MCFTMR 71*4882a593Smuzhiyun #undef CONFIG_MCFPIT 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun /* DSPI and Serial Flash */ 74*4882a593Smuzhiyun #define CONFIG_CF_DSPI 75*4882a593Smuzhiyun #define CONFIG_SF_DEFAULT_SPEED 50000000 76*4882a593Smuzhiyun #define CONFIG_SERIAL_FLASH 77*4882a593Smuzhiyun #define CONFIG_HARD_SPI 78*4882a593Smuzhiyun #define CONFIG_ENV_SPI_BUS 0 79*4882a593Smuzhiyun #define CONFIG_ENV_SPI_CS 1 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun #define CONFIG_SYS_SBFHDR_SIZE 0x7 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun #define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ 84*4882a593Smuzhiyun DSPI_CTAR_PCSSCK_1CLK | \ 85*4882a593Smuzhiyun DSPI_CTAR_PASC(0) | \ 86*4882a593Smuzhiyun DSPI_CTAR_PDT(0) | \ 87*4882a593Smuzhiyun DSPI_CTAR_CSSCK(0) | \ 88*4882a593Smuzhiyun DSPI_CTAR_ASC(0) | \ 89*4882a593Smuzhiyun DSPI_CTAR_DT(1) | \ 90*4882a593Smuzhiyun DSPI_CTAR_BR(6)) 91*4882a593Smuzhiyun #define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0) 92*4882a593Smuzhiyun #define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0) 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun /* Input, PCI, Flexbus, and VCO */ 95*4882a593Smuzhiyun #define CONFIG_EXTRA_CLOCK 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun #define CONFIG_PRAM 2048 /* 2048 KB */ 98*4882a593Smuzhiyun #define CONFIG_SYS_LONGHELP 99*4882a593Smuzhiyun #define CONFIG_AUTO_COMPLETE 100*4882a593Smuzhiyun #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun /* Print Buffer Size */ 103*4882a593Smuzhiyun #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 104*4882a593Smuzhiyun sizeof(CONFIG_SYS_PROMPT) + 16) 105*4882a593Smuzhiyun #define CONFIG_SYS_MAXARGS 16 106*4882a593Smuzhiyun /* Boot Argument Buffer Size */ 107*4882a593Smuzhiyun #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) 110*4882a593Smuzhiyun #define CONFIG_SYS_MBAR 0xFC000000 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun /* 113*4882a593Smuzhiyun * Definitions for initial stack pointer and data area (in internal SRAM) 114*4882a593Smuzhiyun */ 115*4882a593Smuzhiyun #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 116*4882a593Smuzhiyun /* End of used area in internal SRAM */ 117*4882a593Smuzhiyun #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 118*4882a593Smuzhiyun #define CONFIG_SYS_INIT_RAM_CTRL 0x221 119*4882a593Smuzhiyun #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \ 120*4882a593Smuzhiyun GENERATED_GBL_DATA_SIZE) - 32) 121*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 122*4882a593Smuzhiyun #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun /* 125*4882a593Smuzhiyun * Start addresses for the final memory configuration 126*4882a593Smuzhiyun * (Set up by the startup code) 127*4882a593Smuzhiyun * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 128*4882a593Smuzhiyun */ 129*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_BASE 0x40000000 130*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */ 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x400) 133*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 134*4882a593Smuzhiyun #define CONFIG_SYS_DRAM_TEST 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun #if defined(CONFIG_CF_SBF) 137*4882a593Smuzhiyun #define CONFIG_SERIAL_BOOT 138*4882a593Smuzhiyun #endif 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun #if defined(CONFIG_SERIAL_BOOT) 141*4882a593Smuzhiyun #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) 142*4882a593Smuzhiyun #else 143*4882a593Smuzhiyun #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 144*4882a593Smuzhiyun #endif 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun #define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024) 147*4882a593Smuzhiyun /* Reserve 256 kB for Monitor */ 148*4882a593Smuzhiyun #define CONFIG_SYS_MONITOR_LEN (256 << 10) 149*4882a593Smuzhiyun /* Reserve 256 kB for malloc() */ 150*4882a593Smuzhiyun #define CONFIG_SYS_MALLOC_LEN (256 << 10) 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun /* 153*4882a593Smuzhiyun * For booting Linux, the board info and command line data 154*4882a593Smuzhiyun * have to be in the first 8 MB of memory, since this is 155*4882a593Smuzhiyun * the maximum mapped by the Linux kernel during initialization ?? 156*4882a593Smuzhiyun */ 157*4882a593Smuzhiyun /* Initial Memory map for Linux */ 158*4882a593Smuzhiyun #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \ 159*4882a593Smuzhiyun (CONFIG_SYS_SDRAM_SIZE << 20)) 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun /* Configuration for environment 162*4882a593Smuzhiyun * Environment is embedded in u-boot in the second sector of the flash 163*4882a593Smuzhiyun */ 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun #if defined(CONFIG_CF_SBF) 166*4882a593Smuzhiyun #define CONFIG_ENV_IS_IN_SPI_FLASH 1 167*4882a593Smuzhiyun #define CONFIG_ENV_SPI_CS 1 168*4882a593Smuzhiyun #define CONFIG_ENV_OFFSET 0x40000 169*4882a593Smuzhiyun #define CONFIG_ENV_SIZE 0x2000 170*4882a593Smuzhiyun #define CONFIG_ENV_SECT_SIZE 0x10000 171*4882a593Smuzhiyun #endif 172*4882a593Smuzhiyun 173*4882a593Smuzhiyun #undef CONFIG_ENV_OVERWRITE 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun /* Cache Configuration */ 176*4882a593Smuzhiyun #define CONFIG_SYS_CACHELINE_SIZE 16 177*4882a593Smuzhiyun #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 178*4882a593Smuzhiyun CONFIG_SYS_INIT_RAM_SIZE - 8) 179*4882a593Smuzhiyun #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 180*4882a593Smuzhiyun CONFIG_SYS_INIT_RAM_SIZE - 4) 181*4882a593Smuzhiyun #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) 182*4882a593Smuzhiyun #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) 183*4882a593Smuzhiyun #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ 184*4882a593Smuzhiyun CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 185*4882a593Smuzhiyun CF_ACR_EN | CF_ACR_SM_ALL) 186*4882a593Smuzhiyun #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ 187*4882a593Smuzhiyun CF_CACR_ICINVA | CF_CACR_EUSP) 188*4882a593Smuzhiyun #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ 189*4882a593Smuzhiyun CF_CACR_DEC | CF_CACR_DDCM_P | \ 190*4882a593Smuzhiyun CF_CACR_DCINVA) & ~CF_CACR_ICINVA) 191*4882a593Smuzhiyun 192*4882a593Smuzhiyun #define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 193*4882a593Smuzhiyun CONFIG_SYS_INIT_RAM_SIZE - 12) 194*4882a593Smuzhiyun 195*4882a593Smuzhiyun #endif /* __STMARK2_CONFIG_H */ 196