1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2016 3*4882a593Smuzhiyun * Vikas Manocha, <vikas.manocha@st.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __CONFIG_H 9*4882a593Smuzhiyun #define __CONFIG_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_BASE 0x08000000 12*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_ADDR 0x20050000 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #ifdef CONFIG_SUPPORT_SPL 15*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0x08008000 16*4882a593Smuzhiyun #define CONFIG_SYS_LOAD_ADDR 0x08008000 17*4882a593Smuzhiyun #else 18*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE CONFIG_SYS_FLASH_BASE 19*4882a593Smuzhiyun #define CONFIG_SYS_LOAD_ADDR 0xC0400000 20*4882a593Smuzhiyun #define CONFIG_LOADADDR 0xC0400000 21*4882a593Smuzhiyun #endif 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun /* 24*4882a593Smuzhiyun * Configuration of the external SDRAM memory 25*4882a593Smuzhiyun */ 26*4882a593Smuzhiyun #define CONFIG_NR_DRAM_BANKS 1 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define CONFIG_SYS_MAX_FLASH_SECT 8 29*4882a593Smuzhiyun #define CONFIG_SYS_MAX_FLASH_BANKS 1 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define CONFIG_ENV_SIZE (8 << 10) 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define CONFIG_STM32_FLASH 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define CONFIG_DW_GMAC_DEFAULT_DMA_PBL (8) 36*4882a593Smuzhiyun #define CONFIG_DW_ALTDESCRIPTOR 37*4882a593Smuzhiyun #define CONFIG_MII 38*4882a593Smuzhiyun #define CONFIG_PHY_SMSC 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define CONFIG_STM32_HSE_HZ 25000000 41*4882a593Smuzhiyun #define CONFIG_SYS_CLK_FREQ 200000000 /* 200 MHz */ 42*4882a593Smuzhiyun #define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #define CONFIG_CMDLINE_TAG 45*4882a593Smuzhiyun #define CONFIG_SETUP_MEMORY_TAGS 46*4882a593Smuzhiyun #define CONFIG_INITRD_TAG 47*4882a593Smuzhiyun #define CONFIG_REVISION_TAG 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define CONFIG_SYS_CBSIZE 1024 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define CONFIG_BOOTCOMMAND \ 54*4882a593Smuzhiyun "run bootcmd_romfs" 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #define CONFIG_EXTRA_ENV_SETTINGS \ 57*4882a593Smuzhiyun "bootargs_romfs=uclinux.physaddr=0x08180000 root=/dev/mtdblock0\0" \ 58*4882a593Smuzhiyun "bootcmd_romfs=setenv bootargs ${bootargs} ${bootargs_romfs};" \ 59*4882a593Smuzhiyun "bootm 0x08044000 - 0x08042000\0" 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun /* 63*4882a593Smuzhiyun * Command line configuration. 64*4882a593Smuzhiyun */ 65*4882a593Smuzhiyun #define CONFIG_SYS_LONGHELP 66*4882a593Smuzhiyun #define CONFIG_AUTO_COMPLETE 67*4882a593Smuzhiyun #define CONFIG_CMDLINE_EDITING 68*4882a593Smuzhiyun #define CONFIG_CMD_CACHE 69*4882a593Smuzhiyun #define CONFIG_BOARD_LATE_INIT 70*4882a593Smuzhiyun #define CONFIG_DISPLAY_BOARDINFO 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* For SPL */ 73*4882a593Smuzhiyun #ifdef CONFIG_SUPPORT_SPL 74*4882a593Smuzhiyun #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR 75*4882a593Smuzhiyun #define CONFIG_SPL_FRAMEWORK 76*4882a593Smuzhiyun #define CONFIG_SPL_BOARD_INIT 77*4882a593Smuzhiyun #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_FLASH_BASE 78*4882a593Smuzhiyun #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 79*4882a593Smuzhiyun #define CONFIG_SYS_SPL_LEN 0x00008000 80*4882a593Smuzhiyun #define CONFIG_SYS_UBOOT_START 0x080083FD 81*4882a593Smuzhiyun #define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + \ 82*4882a593Smuzhiyun CONFIG_SYS_SPL_LEN) 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun /* DT blob (fdt) address */ 85*4882a593Smuzhiyun #define CONFIG_SYS_FDT_BASE (CONFIG_SYS_FLASH_BASE + \ 86*4882a593Smuzhiyun 0x1C0000) 87*4882a593Smuzhiyun #endif 88*4882a593Smuzhiyun /* For SPL ends */ 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun #endif /* __CONFIG_H */ 91