1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2015 Stefan Roese <sr@denx.de> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun #ifndef __CONFIG_SOCFPGA_SR1500_H__ 7*4882a593Smuzhiyun #define __CONFIG_SOCFPGA_SR1500_H__ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <asm/arch/base_addr_ac5.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define CONFIG_HW_WATCHDOG 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* Memory configurations */ 14*4882a593Smuzhiyun #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SR1500 */ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* Booting Linux */ 17*4882a593Smuzhiyun #define CONFIG_LOADADDR 0x01000000 18*4882a593Smuzhiyun #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* Ethernet on SoC (EMAC) */ 21*4882a593Smuzhiyun #define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII 22*4882a593Smuzhiyun /* The PHY is autodetected, so no MII PHY address is needed here */ 23*4882a593Smuzhiyun #define CONFIG_PHY_MARVELL 24*4882a593Smuzhiyun #define PHY_ANEG_TIMEOUT 8000 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* Environment */ 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* Enable SPI NOR flash reset, needed for SPI booting */ 29*4882a593Smuzhiyun #define CONFIG_SPI_N25Q256A_RESET 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* 32*4882a593Smuzhiyun * Bootcounter 33*4882a593Smuzhiyun */ 34*4882a593Smuzhiyun #define CONFIG_BOOTCOUNT_LIMIT 35*4882a593Smuzhiyun /* last 2 lwords in OCRAM */ 36*4882a593Smuzhiyun #define CONFIG_SYS_BOOTCOUNT_ADDR 0xfffffff8 37*4882a593Smuzhiyun #define CONFIG_SYS_BOOTCOUNT_BE 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* Environment setting for SPI flash */ 40*4882a593Smuzhiyun #define CONFIG_SYS_REDUNDAND_ENVIRONMENT 41*4882a593Smuzhiyun #define CONFIG_ENV_SECT_SIZE (64 * 1024) 42*4882a593Smuzhiyun #define CONFIG_ENV_SIZE (16 * 1024) 43*4882a593Smuzhiyun #define CONFIG_ENV_OFFSET 0x000e0000 44*4882a593Smuzhiyun #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE) 45*4882a593Smuzhiyun #define CONFIG_ENV_SPI_BUS 0 46*4882a593Smuzhiyun #define CONFIG_ENV_SPI_CS 0 47*4882a593Smuzhiyun #define CONFIG_ENV_SPI_MODE SPI_MODE_3 48*4882a593Smuzhiyun #define CONFIG_ENV_SPI_MAX_HZ 100000000 /* Use max of 100MHz */ 49*4882a593Smuzhiyun #define CONFIG_SF_DEFAULT_SPEED 100000000 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* 52*4882a593Smuzhiyun * The QSPI NOR flash layout on SR1500: 53*4882a593Smuzhiyun * 54*4882a593Smuzhiyun * 0000.0000 - 0003.ffff: SPL (4 times) 55*4882a593Smuzhiyun * 0004.0000 - 000d.ffff: U-Boot 56*4882a593Smuzhiyun * 000e.0000 - 000e.ffff: env1 57*4882a593Smuzhiyun * 000f.0000 - 000f.ffff: env2 58*4882a593Smuzhiyun */ 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /* The rest of the configuration is shared */ 61*4882a593Smuzhiyun #include <configs/socfpga_common.h> 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #endif /* __CONFIG_SOCFPGA_SR1500_H__ */ 64