xref: /OK3568_Linux_fs/u-boot/include/configs/socfpga_arria10_socdk.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  *  Copyright (C) 2015-2017 Altera Corporation <www.altera.com>
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * SPDX-License-Identifier:	GPL-2.0
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #ifndef __CONFIG_SOCFGPA_ARRIA10_H__
8*4882a593Smuzhiyun #define __CONFIG_SOCFGPA_ARRIA10_H__
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #include <asm/arch/base_addr_a10.h>
11*4882a593Smuzhiyun 
12*4882a593Smuzhiyun #define CONFIG_HW_WATCHDOG
13*4882a593Smuzhiyun 
14*4882a593Smuzhiyun /* Booting Linux */
15*4882a593Smuzhiyun #define CONFIG_LOADADDR		0x01000000
16*4882a593Smuzhiyun #define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun /*
19*4882a593Smuzhiyun  * U-Boot general configurations
20*4882a593Smuzhiyun  */
21*4882a593Smuzhiyun /* Cache options */
22*4882a593Smuzhiyun #define CONFIG_SYS_DCACHE_OFF
23*4882a593Smuzhiyun 
24*4882a593Smuzhiyun /* Memory configurations  */
25*4882a593Smuzhiyun #define PHYS_SDRAM_1_SIZE		0x40000000
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun /* Ethernet on SoC (EMAC) */
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun /*
30*4882a593Smuzhiyun  * U-Boot environment configurations
31*4882a593Smuzhiyun  */
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun /*
34*4882a593Smuzhiyun  * Serial / UART configurations
35*4882a593Smuzhiyun  */
36*4882a593Smuzhiyun #define CONFIG_SYS_NS16550_MEM32
37*4882a593Smuzhiyun #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun /*
40*4882a593Smuzhiyun  * L4 OSC1 Timer 0
41*4882a593Smuzhiyun  */
42*4882a593Smuzhiyun /* reload value when timer count to zero */
43*4882a593Smuzhiyun #define TIMER_LOAD_VAL			0xFFFFFFFF
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun /*
46*4882a593Smuzhiyun  * Flash configurations
47*4882a593Smuzhiyun  */
48*4882a593Smuzhiyun #define CONFIG_SYS_MAX_FLASH_BANKS     1
49*4882a593Smuzhiyun 
50*4882a593Smuzhiyun /* The rest of the configuration is shared */
51*4882a593Smuzhiyun #include <configs/socfpga_common.h>
52*4882a593Smuzhiyun 
53*4882a593Smuzhiyun #endif	/* __CONFIG_SOCFGPA_ARRIA10_H__ */
54