1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Bluewater Systems Snapper 9260 and 9G20 modules 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * (C) Copyright 2011 Bluewater Systems 5*4882a593Smuzhiyun * Author: Andre Renaud <andre@bluewatersys.com> 6*4882a593Smuzhiyun * Author: Ryan Mallon <ryan@bluewatersys.com> 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef __CONFIG_H 12*4882a593Smuzhiyun #define __CONFIG_H 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* SoC type is defined in boards.cfg */ 15*4882a593Smuzhiyun #include <asm/hardware.h> 16*4882a593Smuzhiyun #include <linux/sizes.h> 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0x21f00000 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* ARM asynchronous clock */ 21*4882a593Smuzhiyun #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* External Crystal, in Hz */ 22*4882a593Smuzhiyun #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* CPU */ 25*4882a593Smuzhiyun #define CONFIG_ARCH_CPU_INIT 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 28*4882a593Smuzhiyun #define CONFIG_SETUP_MEMORY_TAGS 29*4882a593Smuzhiyun #define CONFIG_INITRD_TAG 30*4882a593Smuzhiyun #define CONFIG_SKIP_LOWLEVEL_INIT 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* SDRAM */ 33*4882a593Smuzhiyun #define CONFIG_NR_DRAM_BANKS 1 34*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 35*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) /* 64MB */ 36*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_ADDR (ATMEL_BASE_SRAM1 + 0x1000 - \ 37*4882a593Smuzhiyun GENERATED_GBL_DATA_SIZE) 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* Mem test settings */ 40*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 41*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + (1024 * 1024)) 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* NAND Flash */ 44*4882a593Smuzhiyun #define CONFIG_SYS_MAX_NAND_DEVICE 1 45*4882a593Smuzhiyun #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 46*4882a593Smuzhiyun #define CONFIG_SYS_NAND_DBW_8 47*4882a593Smuzhiyun #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* AD21 */ 48*4882a593Smuzhiyun #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* AD22 */ 49*4882a593Smuzhiyun #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 50*4882a593Smuzhiyun #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* Ethernet */ 53*4882a593Smuzhiyun #define CONFIG_MACB 54*4882a593Smuzhiyun #define CONFIG_RMII 55*4882a593Smuzhiyun #define CONFIG_NET_RETRY_COUNT 20 56*4882a593Smuzhiyun #define CONFIG_RESET_PHY_R 57*4882a593Smuzhiyun #define CONFIG_AT91_WANTS_COMMON_PHY 58*4882a593Smuzhiyun #define CONFIG_TFTP_PORT 59*4882a593Smuzhiyun #define CONFIG_TFTP_TSIZE 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* USB */ 62*4882a593Smuzhiyun #define CONFIG_USB_ATMEL 63*4882a593Smuzhiyun #define CONFIG_USB_ATMEL_CLK_SEL_PLLB 64*4882a593Smuzhiyun #define CONFIG_USB_OHCI_NEW 65*4882a593Smuzhiyun #define CONFIG_SYS_USB_OHCI_CPU_INIT 66*4882a593Smuzhiyun #define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_UHP_BASE 67*4882a593Smuzhiyun #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260" 68*4882a593Smuzhiyun #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun /* GPIOs and IO expander */ 71*4882a593Smuzhiyun #define CONFIG_ATMEL_LEGACY 72*4882a593Smuzhiyun #define CONFIG_AT91_GPIO 73*4882a593Smuzhiyun #define CONFIG_AT91_GPIO_PULLUP 1 74*4882a593Smuzhiyun #define CONFIG_PCA953X 75*4882a593Smuzhiyun #define CONFIG_SYS_I2C_PCA953X_ADDR 0x28 76*4882a593Smuzhiyun #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x28, 16} } 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun /* UARTs/Serial console */ 79*4882a593Smuzhiyun #define CONFIG_ATMEL_USART 80*4882a593Smuzhiyun #ifndef CONFIG_DM_SERIAL 81*4882a593Smuzhiyun #define CONFIG_USART_BASE ATMEL_BASE_DBGU 82*4882a593Smuzhiyun #define CONFIG_USART_ID ATMEL_ID_SYS 83*4882a593Smuzhiyun #endif 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun /* I2C - Bit-bashed */ 86*4882a593Smuzhiyun #define CONFIG_SYS_I2C 87*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ 88*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SOFT_SPEED 100000 89*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F 90*4882a593Smuzhiyun #define CONFIG_SOFT_I2C_READ_REPEATED_START 91*4882a593Smuzhiyun #define I2C_INIT do { \ 92*4882a593Smuzhiyun at91_set_gpio_output(AT91_PIN_PA23, 1); \ 93*4882a593Smuzhiyun at91_set_gpio_output(AT91_PIN_PA24, 1); \ 94*4882a593Smuzhiyun at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \ 95*4882a593Smuzhiyun at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \ 96*4882a593Smuzhiyun } while (0) 97*4882a593Smuzhiyun #define I2C_SOFT_DECLARATIONS 98*4882a593Smuzhiyun #define I2C_ACTIVE 99*4882a593Smuzhiyun #define I2C_TRISTATE at91_set_gpio_input(AT91_PIN_PA23, 1); 100*4882a593Smuzhiyun #define I2C_READ at91_get_gpio_value(AT91_PIN_PA23); 101*4882a593Smuzhiyun #define I2C_SDA(bit) do { \ 102*4882a593Smuzhiyun if (bit) { \ 103*4882a593Smuzhiyun at91_set_gpio_input(AT91_PIN_PA23, 1); \ 104*4882a593Smuzhiyun } else { \ 105*4882a593Smuzhiyun at91_set_gpio_output(AT91_PIN_PA23, 1); \ 106*4882a593Smuzhiyun at91_set_gpio_value(AT91_PIN_PA23, bit); \ 107*4882a593Smuzhiyun } \ 108*4882a593Smuzhiyun } while (0) 109*4882a593Smuzhiyun #define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTA, 24, bit) 110*4882a593Smuzhiyun #define I2C_DELAY udelay(2) 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun /* Boot options */ 113*4882a593Smuzhiyun #define CONFIG_SYS_LOAD_ADDR 0x23000000 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun #define CONFIG_BOOTP_BOOTFILESIZE 116*4882a593Smuzhiyun #define CONFIG_BOOTP_BOOTPATH 117*4882a593Smuzhiyun #define CONFIG_BOOTP_GATEWAY 118*4882a593Smuzhiyun #define CONFIG_BOOTP_HOSTNAME 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun /* Environment settings */ 121*4882a593Smuzhiyun #define CONFIG_ENV_OFFSET (512 << 10) 122*4882a593Smuzhiyun #define CONFIG_ENV_SIZE (256 << 10) 123*4882a593Smuzhiyun #define CONFIG_ENV_OVERWRITE 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun /* Console settings */ 126*4882a593Smuzhiyun #define CONFIG_SYS_LONGHELP 127*4882a593Smuzhiyun #define CONFIG_CMDLINE_EDITING 128*4882a593Smuzhiyun #define CONFIG_AUTO_COMPLETE 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun /* U-Boot memory settings */ 131*4882a593Smuzhiyun #define CONFIG_SYS_MALLOC_LEN (1 << 20) 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun #endif /* __CONFIG_H */ 134