1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * include/configs/silk.h 3*4882a593Smuzhiyun * This file is silk board configuration. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2015 Renesas Electronics Corporation 6*4882a593Smuzhiyun * Copyright (C) 2015 Cogent Embedded, Inc. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef __SILK_H 12*4882a593Smuzhiyun #define __SILK_H 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #undef DEBUG 15*4882a593Smuzhiyun #define CONFIG_R8A7794 16*4882a593Smuzhiyun #define CONFIG_ARCH_RMOBILE_BOARD_STRING "Silk" 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #include "rcar-gen2-common.h" 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT) 21*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0x70000000 22*4882a593Smuzhiyun #else 23*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0xE6304000 24*4882a593Smuzhiyun #endif 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT) 27*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC 28*4882a593Smuzhiyun #else 29*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_ADDR 0xE633FFFC 30*4882a593Smuzhiyun #endif 31*4882a593Smuzhiyun #define STACK_AREA_SIZE 0xC000 32*4882a593Smuzhiyun #define LOW_LEVEL_MERAM_STACK \ 33*4882a593Smuzhiyun (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* MEMORY */ 36*4882a593Smuzhiyun #define RCAR_GEN2_SDRAM_BASE 0x40000000 37*4882a593Smuzhiyun #define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024) 38*4882a593Smuzhiyun #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* FLASH */ 41*4882a593Smuzhiyun #define CONFIG_SPI_FLASH_QUAD 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* SH Ether */ 44*4882a593Smuzhiyun #define CONFIG_SH_ETHER 45*4882a593Smuzhiyun #define CONFIG_SH_ETHER_USE_PORT 0 46*4882a593Smuzhiyun #define CONFIG_SH_ETHER_PHY_ADDR 0x1 47*4882a593Smuzhiyun #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII 48*4882a593Smuzhiyun #define CONFIG_SH_ETHER_CACHE_WRITEBACK 49*4882a593Smuzhiyun #define CONFIG_SH_ETHER_CACHE_INVALIDATE 50*4882a593Smuzhiyun #define CONFIG_SH_ETHER_ALIGNE_SIZE 64 51*4882a593Smuzhiyun #define CONFIG_BITBANGMII 52*4882a593Smuzhiyun #define CONFIG_BITBANGMII_MULTI 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* Board Clock */ 55*4882a593Smuzhiyun #define RMOBILE_XTAL_CLK 20000000u 56*4882a593Smuzhiyun #define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK 57*4882a593Smuzhiyun #define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */ 58*4882a593Smuzhiyun #define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2) 59*4882a593Smuzhiyun #define CONFIG_P_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 24) 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #define CONFIG_SYS_TMU_CLK_DIV 4 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun /* i2c */ 64*4882a593Smuzhiyun #define CONFIG_SYS_I2C 65*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SH 66*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SLAVE 0x7F 67*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3 68*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SH_SPEED0 400000 69*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SH_SPEED1 400000 70*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SH_SPEED2 400000 71*4882a593Smuzhiyun #define CONFIG_SH_I2C_DATA_HIGH 4 72*4882a593Smuzhiyun #define CONFIG_SH_I2C_DATA_LOW 5 73*4882a593Smuzhiyun #define CONFIG_SH_I2C_CLOCK 10000000 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun #define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */ 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun /* USB */ 78*4882a593Smuzhiyun #define CONFIG_USB_EHCI_RMOBILE 79*4882a593Smuzhiyun #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun /* MMCIF */ 82*4882a593Smuzhiyun #define CONFIG_SH_MMCIF 83*4882a593Smuzhiyun #define CONFIG_SH_MMCIF_ADDR 0xee200000 84*4882a593Smuzhiyun #define CONFIG_SH_MMCIF_CLK 48000000 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun /* SDHI */ 87*4882a593Smuzhiyun #define CONFIG_SH_SDHI_FREQ 97500000 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun /* Module stop status bits */ 90*4882a593Smuzhiyun /* INTC-RT */ 91*4882a593Smuzhiyun #define CONFIG_SMSTP0_ENA 0x00400000 92*4882a593Smuzhiyun /* MSIF */ 93*4882a593Smuzhiyun #define CONFIG_SMSTP2_ENA 0x00002000 94*4882a593Smuzhiyun /* INTC-SYS, IRQC */ 95*4882a593Smuzhiyun #define CONFIG_SMSTP4_ENA 0x00000180 96*4882a593Smuzhiyun /* SCIF2 */ 97*4882a593Smuzhiyun #define CONFIG_SMSTP7_ENA 0x00080000 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun #endif /* __SILK_H */ 100