1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Configuation settings for shmin (T-SH7706LAN, T-SH7706LSR) 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2010, 2011 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __SHMIN_H 10*4882a593Smuzhiyun #define __SHMIN_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define CONFIG_CPU_SH7706 1 13*4882a593Smuzhiyun /* T-SH7706LAN */ 14*4882a593Smuzhiyun #define CONFIG_SHMIN 1 15*4882a593Smuzhiyun /* T-SH7706LSR*/ 16*4882a593Smuzhiyun /* #define CONFIG_T_SH7706LSR 1 */ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* 19*4882a593Smuzhiyun * This board has original boot loader. If you write u-boot to 0x0, 20*4882a593Smuzhiyun * you should set undef. 21*4882a593Smuzhiyun */ 22*4882a593Smuzhiyun #undef CONFIG_SHOW_BOOT_PROGRESS 23*4882a593Smuzhiyun #define CONFIG_DISPLAY_BOARDINFO 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* system */ 26*4882a593Smuzhiyun #define SHMIN_SDRAM_BASE (0x8C000000) 27*4882a593Smuzhiyun #define SHMIN_FLASH_BASE_1 (0xA0000000) 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0x8DFB0000 30*4882a593Smuzhiyun #define CONFIG_SYS_LONGHELP /* undef to save memory */ 31*4882a593Smuzhiyun #define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */ 32*4882a593Smuzhiyun /* List of legal baudrate settings for this board */ 33*4882a593Smuzhiyun #define CONFIG_SYS_BAUDRATE_TABLE { 9600,14400,19200,38400,57600,115200 } 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* SCIF */ 36*4882a593Smuzhiyun #define CONFIG_CONS_SCIF0 1 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* memory */ 39*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_BASE SHMIN_SDRAM_BASE 40*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_SIZE (32 * 1024 * 1024) 41*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_START SHMIN_SDRAM_BASE 42*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - (256 * 1024)) 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 1 * 1024 * 1024) 45*4882a593Smuzhiyun #define CONFIG_SYS_MONITOR_BASE (SHMIN_FLASH_BASE_1 + CONFIG_ENV_SECT_SIZE) 46*4882a593Smuzhiyun #define CONFIG_SYS_MONITOR_LEN (128 * 1024) 47*4882a593Smuzhiyun #define CONFIG_SYS_MALLOC_LEN (256 * 1024) 48*4882a593Smuzhiyun #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* FLASH */ 51*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_CFI 52*4882a593Smuzhiyun #define CONFIG_FLASH_CFI_DRIVER 53*4882a593Smuzhiyun #undef CONFIG_SYS_FLASH_QUIET_TEST 54*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ 55*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_BASE SHMIN_FLASH_BASE_1 56*4882a593Smuzhiyun #define CONFIG_SYS_MAX_FLASH_SECT 11 57*4882a593Smuzhiyun #define CONFIG_SYS_MAX_FLASH_BANKS 1 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define CONFIG_FLASH_CFI_LEGACY 60*4882a593Smuzhiyun #define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_FLASH_BASE 61*4882a593Smuzhiyun #define CONFIG_SYS_ATMEL_TOTALSECT CONFIG_SYS_MAX_FLASH_SECT 62*4882a593Smuzhiyun #define CONFIG_SYS_ATMEL_REGION 4 63*4882a593Smuzhiyun #define CONFIG_SYS_ATMEL_SECT {1, 2, 1, 7} 64*4882a593Smuzhiyun #define CONFIG_SYS_ATMEL_SECTSZ {0x4000, 0x2000, 0x8000, 0x10000} 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #define CONFIG_ENV_SECT_SIZE (64 * 1024) 67*4882a593Smuzhiyun #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #ifdef CONFIG_T_SH7706LSR 70*4882a593Smuzhiyun #define CONFIG_ENV_ADDR (SHMIN_FLASH_BASE_1 + 70000) 71*4882a593Smuzhiyun #else 72*4882a593Smuzhiyun #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 73*4882a593Smuzhiyun #endif 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 76*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_WRITE_TOUT 500 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun /* Board Clock */ 79*4882a593Smuzhiyun #ifdef CONFIG_T_SH7706LSR 80*4882a593Smuzhiyun #define CONFIG_SYS_CLK_FREQ 40000000 81*4882a593Smuzhiyun #else 82*4882a593Smuzhiyun #define CONFIG_SYS_CLK_FREQ 33333333 83*4882a593Smuzhiyun #endif /* CONFIG_T_SH7706LSR */ 84*4882a593Smuzhiyun #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ 85*4882a593Smuzhiyun #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 86*4882a593Smuzhiyun #define CONFIG_SYS_TMU_CLK_DIV 4 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun /* Network device */ 89*4882a593Smuzhiyun #define CONFIG_DRIVER_NE2000 90*4882a593Smuzhiyun #define CONFIG_DRIVER_NE2000_BASE (0xb0000300) 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun #endif /* __SHMIN_H */ 93