1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Configuation settings for the sh7757lcr board 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2011 Renesas Solutions Corp. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __SH7757LCR_H 10*4882a593Smuzhiyun #define __SH7757LCR_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define CONFIG_CPU_SH7757 1 13*4882a593Smuzhiyun #define CONFIG_SH7757LCR 1 14*4882a593Smuzhiyun #define CONFIG_SH7757LCR_DDR_ECC 1 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0x8ef80000 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define CONFIG_DISPLAY_BOARDINFO 19*4882a593Smuzhiyun #undef CONFIG_SHOW_BOOT_PROGRESS 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* MEMORY */ 22*4882a593Smuzhiyun #define SH7757LCR_SDRAM_BASE (0x80000000) 23*4882a593Smuzhiyun #define SH7757LCR_SDRAM_SIZE (240 * 1024 * 1024) 24*4882a593Smuzhiyun #define SH7757LCR_SDRAM_ECC_SETTING 0x0f000000 /* 240MByte */ 25*4882a593Smuzhiyun #define SH7757LCR_SDRAM_DVC_SIZE (16 * 1024 * 1024) 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define CONFIG_SYS_LONGHELP 28*4882a593Smuzhiyun #define CONFIG_SYS_PBSIZE 256 29*4882a593Smuzhiyun #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* SCIF */ 32*4882a593Smuzhiyun #define CONFIG_CONS_SCIF2 1 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_START (SH7757LCR_SDRAM_BASE) 35*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ 36*4882a593Smuzhiyun 224 * 1024 * 1024) 37*4882a593Smuzhiyun #undef CONFIG_SYS_ALT_MEMTEST 38*4882a593Smuzhiyun #undef CONFIG_SYS_MEMTEST_SCRATCH 39*4882a593Smuzhiyun #undef CONFIG_SYS_LOADS_BAUD_CHANGE 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_BASE (SH7757LCR_SDRAM_BASE) 42*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_SIZE (SH7757LCR_SDRAM_SIZE) 43*4882a593Smuzhiyun #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \ 44*4882a593Smuzhiyun (128 + 16) * 1024 * 1024) 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define CONFIG_SYS_MONITOR_BASE 0x00000000 47*4882a593Smuzhiyun #define CONFIG_SYS_MONITOR_LEN (256 * 1024) 48*4882a593Smuzhiyun #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 49*4882a593Smuzhiyun #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* Ether */ 52*4882a593Smuzhiyun #define CONFIG_SH_ETHER 1 53*4882a593Smuzhiyun #define CONFIG_SH_ETHER_USE_PORT 0 54*4882a593Smuzhiyun #define CONFIG_SH_ETHER_PHY_ADDR 1 55*4882a593Smuzhiyun #define CONFIG_SH_ETHER_CACHE_WRITEBACK 1 56*4882a593Smuzhiyun #define CONFIG_BITBANGMII 57*4882a593Smuzhiyun #define CONFIG_BITBANGMII_MULTI 58*4882a593Smuzhiyun #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #define SH7757LCR_ETHERNET_MAC_BASE_SPI 0x000b0000 61*4882a593Smuzhiyun #define SH7757LCR_SPI_SECTOR_SIZE (64 * 1024) 62*4882a593Smuzhiyun #define SH7757LCR_ETHERNET_MAC_BASE SH7757LCR_ETHERNET_MAC_BASE_SPI 63*4882a593Smuzhiyun #define SH7757LCR_ETHERNET_MAC_SIZE 17 64*4882a593Smuzhiyun #define SH7757LCR_ETHERNET_NUM_CH 2 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun /* Gigabit Ether */ 67*4882a593Smuzhiyun #define SH7757LCR_GIGA_ETHERNET_NUM_CH 2 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun /* SPI */ 70*4882a593Smuzhiyun #define CONFIG_SH_SPI_BASE 0xfe002000 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* MMCIF */ 73*4882a593Smuzhiyun #define CONFIG_SH_MMCIF 1 74*4882a593Smuzhiyun #define CONFIG_SH_MMCIF_ADDR 0xffcb0000 75*4882a593Smuzhiyun #define CONFIG_SH_MMCIF_CLK 48000000 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun /* SH7757 board */ 78*4882a593Smuzhiyun #define SH7757LCR_SDRAM_PHYS_TOP 0x40000000 79*4882a593Smuzhiyun #define SH7757LCR_GRA_OFFSET 0x1f000000 80*4882a593Smuzhiyun #define SH7757LCR_PCIEBRG_ADDR_B0 0x000a0000 81*4882a593Smuzhiyun #define SH7757LCR_PCIEBRG_SIZE_B0 (64 * 1024) 82*4882a593Smuzhiyun #define SH7757LCR_PCIEBRG_ADDR 0x00090000 83*4882a593Smuzhiyun #define SH7757LCR_PCIEBRG_SIZE (96 * 1024) 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun /* ENV setting */ 86*4882a593Smuzhiyun #define CONFIG_ENV_IS_EMBEDDED 87*4882a593Smuzhiyun #define CONFIG_ENV_SECT_SIZE (64 * 1024) 88*4882a593Smuzhiyun #define CONFIG_ENV_ADDR (0x00080000) 89*4882a593Smuzhiyun #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR) 90*4882a593Smuzhiyun #define CONFIG_ENV_OVERWRITE 1 91*4882a593Smuzhiyun #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 92*4882a593Smuzhiyun #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) 93*4882a593Smuzhiyun #define CONFIG_EXTRA_ENV_SETTINGS \ 94*4882a593Smuzhiyun "netboot=bootp; bootm\0" 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun /* Board Clock */ 97*4882a593Smuzhiyun #define CONFIG_SYS_CLK_FREQ 48000000 98*4882a593Smuzhiyun #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ 99*4882a593Smuzhiyun #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 100*4882a593Smuzhiyun #define CONFIG_SYS_TMU_CLK_DIV 4 101*4882a593Smuzhiyun #endif /* __SH7757LCR_H */ 102