1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Configuation settings for the sh7752evb board 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2012 Renesas Solutions Corp. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __SH7752EVB_H 10*4882a593Smuzhiyun #define __SH7752EVB_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define CONFIG_CPU_SH7752 1 13*4882a593Smuzhiyun #define CONFIG_SH7752EVB 1 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0x5ff80000 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define CONFIG_DISPLAY_BOARDINFO 18*4882a593Smuzhiyun #undef CONFIG_SHOW_BOOT_PROGRESS 19*4882a593Smuzhiyun #define CONFIG_CMDLINE_EDITING 20*4882a593Smuzhiyun #define CONFIG_AUTO_COMPLETE 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* MEMORY */ 23*4882a593Smuzhiyun #define SH7752EVB_SDRAM_BASE (0x40000000) 24*4882a593Smuzhiyun #define SH7752EVB_SDRAM_SIZE (512 * 1024 * 1024) 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define CONFIG_SYS_LONGHELP 27*4882a593Smuzhiyun #define CONFIG_SYS_PBSIZE 256 28*4882a593Smuzhiyun #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* SCIF */ 31*4882a593Smuzhiyun #define CONFIG_CONS_SCIF2 1 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_START (SH7752EVB_SDRAM_BASE) 34*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ 35*4882a593Smuzhiyun 480 * 1024 * 1024) 36*4882a593Smuzhiyun #undef CONFIG_SYS_ALT_MEMTEST 37*4882a593Smuzhiyun #undef CONFIG_SYS_MEMTEST_SCRATCH 38*4882a593Smuzhiyun #undef CONFIG_SYS_LOADS_BAUD_CHANGE 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_BASE (SH7752EVB_SDRAM_BASE) 41*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_SIZE (SH7752EVB_SDRAM_SIZE) 42*4882a593Smuzhiyun #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \ 43*4882a593Smuzhiyun 128 * 1024 * 1024) 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define CONFIG_SYS_MONITOR_BASE 0x00000000 46*4882a593Smuzhiyun #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 47*4882a593Smuzhiyun #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 48*4882a593Smuzhiyun #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* Ether */ 51*4882a593Smuzhiyun #define CONFIG_SH_ETHER 1 52*4882a593Smuzhiyun #define CONFIG_SH_ETHER_USE_PORT 0 53*4882a593Smuzhiyun #define CONFIG_SH_ETHER_PHY_ADDR 18 54*4882a593Smuzhiyun #define CONFIG_SH_ETHER_CACHE_WRITEBACK 1 55*4882a593Smuzhiyun #define CONFIG_SH_ETHER_USE_GETHER 1 56*4882a593Smuzhiyun #define CONFIG_BITBANGMII 57*4882a593Smuzhiyun #define CONFIG_BITBANGMII_MULTI 58*4882a593Smuzhiyun #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII 59*4882a593Smuzhiyun #define CONFIG_PHY_VITESSE 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #define SH7752EVB_ETHERNET_MAC_BASE_SPI 0x00090000 62*4882a593Smuzhiyun #define SH7752EVB_SPI_SECTOR_SIZE (64 * 1024) 63*4882a593Smuzhiyun #define SH7752EVB_ETHERNET_MAC_BASE SH7752EVB_ETHERNET_MAC_BASE_SPI 64*4882a593Smuzhiyun #define SH7752EVB_ETHERNET_MAC_SIZE 17 65*4882a593Smuzhiyun #define SH7752EVB_ETHERNET_NUM_CH 2 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun /* SPI */ 68*4882a593Smuzhiyun #define CONFIG_SH_SPI_BASE 0xfe002000 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun /* MMCIF */ 71*4882a593Smuzhiyun #define CONFIG_SH_MMCIF 1 72*4882a593Smuzhiyun #define CONFIG_SH_MMCIF_ADDR 0xffcb0000 73*4882a593Smuzhiyun #define CONFIG_SH_MMCIF_CLK 48000000 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun /* ENV setting */ 76*4882a593Smuzhiyun #define CONFIG_ENV_IS_EMBEDDED 77*4882a593Smuzhiyun #define CONFIG_ENV_SECT_SIZE (64 * 1024) 78*4882a593Smuzhiyun #define CONFIG_ENV_ADDR (0x00080000) 79*4882a593Smuzhiyun #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR) 80*4882a593Smuzhiyun #define CONFIG_ENV_OVERWRITE 1 81*4882a593Smuzhiyun #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 82*4882a593Smuzhiyun #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) 83*4882a593Smuzhiyun #define CONFIG_EXTRA_ENV_SETTINGS \ 84*4882a593Smuzhiyun "netboot=bootp; bootm\0" 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun /* Board Clock */ 87*4882a593Smuzhiyun #define CONFIG_SYS_CLK_FREQ 48000000 88*4882a593Smuzhiyun #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ 89*4882a593Smuzhiyun #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 90*4882a593Smuzhiyun #define CONFIG_SYS_TMU_CLK_DIV 4 91*4882a593Smuzhiyun #endif /* __SH7752EVB_H */ 92