1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Configuration settings for the SAMA5D3 Xplained board. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2014 Atmel Corporation 5*4882a593Smuzhiyun * Bo Shen <voice.shen@atmel.com> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __CONFIG_H 11*4882a593Smuzhiyun #define __CONFIG_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include "at91-sama5_common.h" 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* 16*4882a593Smuzhiyun * This needs to be defined for the OHCI code to work but it is defined as 17*4882a593Smuzhiyun * ATMEL_ID_UHPHS in the CPU specific header files. 18*4882a593Smuzhiyun */ 19*4882a593Smuzhiyun #define ATMEL_ID_UHP ATMEL_ID_UHPHS 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* 22*4882a593Smuzhiyun * Specify the clock enable bit in the PMC_SCER register. 23*4882a593Smuzhiyun */ 24*4882a593Smuzhiyun #define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* SDRAM */ 27*4882a593Smuzhiyun #define CONFIG_NR_DRAM_BANKS 1 28*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS 29*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_SIZE 0x10000000 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #ifdef CONFIG_SPL_BUILD 32*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_ADDR 0x318000 33*4882a593Smuzhiyun #else 34*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_ADDR \ 35*4882a593Smuzhiyun (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) 36*4882a593Smuzhiyun #endif 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* NAND flash */ 39*4882a593Smuzhiyun #ifdef CONFIG_CMD_NAND 40*4882a593Smuzhiyun #define CONFIG_SYS_MAX_NAND_DEVICE 1 41*4882a593Smuzhiyun #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 42*4882a593Smuzhiyun /* our ALE is AD21 */ 43*4882a593Smuzhiyun #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) 44*4882a593Smuzhiyun /* our CLE is AD22 */ 45*4882a593Smuzhiyun #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) 46*4882a593Smuzhiyun #define CONFIG_SYS_NAND_ONFI_DETECTION 47*4882a593Smuzhiyun #endif 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* USB */ 50*4882a593Smuzhiyun #ifdef CONFIG_CMD_USB 51*4882a593Smuzhiyun #define CONFIG_USB_ATMEL 52*4882a593Smuzhiyun #define CONFIG_USB_ATMEL_CLK_SEL_UPLL 53*4882a593Smuzhiyun #define CONFIG_USB_OHCI_NEW 54*4882a593Smuzhiyun #define CONFIG_SYS_USB_OHCI_CPU_INIT 55*4882a593Smuzhiyun #define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI 56*4882a593Smuzhiyun #define CONFIG_SYS_USB_OHCI_SLOT_NAME "SAMA5D3 Xplained" 57*4882a593Smuzhiyun #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 58*4882a593Smuzhiyun #endif 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun #if CONFIG_SYS_USE_NANDFLASH 63*4882a593Smuzhiyun /* override the bootcmd, bootargs and other configuration for nandflash env */ 64*4882a593Smuzhiyun #elif CONFIG_SYS_USE_MMC 65*4882a593Smuzhiyun /* override the bootcmd, bootargs and other configuration for sd/mmc env */ 66*4882a593Smuzhiyun #endif 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun /* SPL */ 69*4882a593Smuzhiyun #define CONFIG_SPL_FRAMEWORK 70*4882a593Smuzhiyun #define CONFIG_SPL_TEXT_BASE 0x300000 71*4882a593Smuzhiyun #define CONFIG_SPL_MAX_SIZE 0x18000 72*4882a593Smuzhiyun #define CONFIG_SPL_BSS_START_ADDR 0x20000000 73*4882a593Smuzhiyun #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 74*4882a593Smuzhiyun #define CONFIG_SYS_SPL_MALLOC_START 0x20080000 75*4882a593Smuzhiyun #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun #define CONFIG_SYS_MONITOR_LEN (512 << 10) 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun #ifdef CONFIG_SYS_USE_MMC 80*4882a593Smuzhiyun #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 81*4882a593Smuzhiyun #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun #elif CONFIG_SYS_USE_NANDFLASH 84*4882a593Smuzhiyun #define CONFIG_SPL_NAND_DRIVERS 85*4882a593Smuzhiyun #define CONFIG_SPL_NAND_BASE 86*4882a593Smuzhiyun #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 87*4882a593Smuzhiyun #define CONFIG_SYS_NAND_5_ADDR_CYCLE 88*4882a593Smuzhiyun #define CONFIG_SYS_NAND_PAGE_SIZE 0x800 89*4882a593Smuzhiyun #define CONFIG_SYS_NAND_PAGE_COUNT 64 90*4882a593Smuzhiyun #define CONFIG_SYS_NAND_OOBSIZE 64 91*4882a593Smuzhiyun #define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 92*4882a593Smuzhiyun #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun #endif 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun #endif 97