1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Configuration file for the SAMA5D2 PTC EK Board. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2017 Microchip Technology Inc. 6*4882a593Smuzhiyun * Wenyou Yang <wenyou.yang@microchip.com> 7*4882a593Smuzhiyun * Ludovic Desroches <ludovic.desroches@microchip.com> 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __CONFIG_H 11*4882a593Smuzhiyun #define __CONFIG_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include "at91-sama5_common.h" 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #undef CONFIG_SYS_AT91_MAIN_CLOCK 16*4882a593Smuzhiyun #define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define CONFIG_MISC_INIT_R 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* SDRAM */ 21*4882a593Smuzhiyun #define CONFIG_NR_DRAM_BANKS 1 22*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_BASE 0x20000000 23*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_SIZE 0x20000000 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_ADDR \ 26*4882a593Smuzhiyun (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* NAND Flash */ 31*4882a593Smuzhiyun #ifdef CONFIG_CMD_NAND 32*4882a593Smuzhiyun #define CONFIG_SYS_MAX_NAND_DEVICE 1 33*4882a593Smuzhiyun #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 34*4882a593Smuzhiyun /* our ALE is AD21 */ 35*4882a593Smuzhiyun #define CONFIG_SYS_NAND_MASK_ALE BIT(21) 36*4882a593Smuzhiyun /* our CLE is AD22 */ 37*4882a593Smuzhiyun #define CONFIG_SYS_NAND_MASK_CLE BIT(22) 38*4882a593Smuzhiyun #define CONFIG_SYS_NAND_ONFI_DETECTION 39*4882a593Smuzhiyun #endif 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #endif /* __CONFIG_H */ 42