1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Configuration settings for the SAMA5D2 PTC Engineering board. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2016 Atmel 5*4882a593Smuzhiyun * Wenyou Yang <wenyou.yang@atmel.com> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __CONFIG_H 11*4882a593Smuzhiyun #define __CONFIG_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include "at91-sama5_common.h" 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* serial console */ 16*4882a593Smuzhiyun #define CONFIG_ATMEL_USART 17*4882a593Smuzhiyun #define CONFIG_USART_BASE ATMEL_BASE_UART0 18*4882a593Smuzhiyun #define CONFIG_USART_ID ATMEL_ID_UART0 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS 21*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_SIZE 0x20000000 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #ifdef CONFIG_SPL_BUILD 24*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_ADDR 0x210000 25*4882a593Smuzhiyun #else 26*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_ADDR \ 27*4882a593Smuzhiyun (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) 28*4882a593Smuzhiyun #endif 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #undef CONFIG_AT91_GPIO 33*4882a593Smuzhiyun #define CONFIG_ATMEL_PIO4 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* SDRAM */ 36*4882a593Smuzhiyun #define CONFIG_NR_DRAM_BANKS 1 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* SerialFlash */ 39*4882a593Smuzhiyun #ifdef CONFIG_CMD_SF 40*4882a593Smuzhiyun #define CONFIG_ATMEL_SPI 41*4882a593Smuzhiyun #define CONFIG_SPI_FLASH_ATMEL 42*4882a593Smuzhiyun #define CONFIG_SF_DEFAULT_BUS 0 43*4882a593Smuzhiyun #define CONFIG_SF_DEFAULT_CS 0 44*4882a593Smuzhiyun #define CONFIG_SF_DEFAULT_SPEED 30000000 45*4882a593Smuzhiyun #endif 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* NAND flash */ 48*4882a593Smuzhiyun #ifdef CONFIG_CMD_NAND 49*4882a593Smuzhiyun #define CONFIG_NAND_ATMEL 50*4882a593Smuzhiyun #define CONFIG_SYS_MAX_NAND_DEVICE 1 51*4882a593Smuzhiyun #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 52*4882a593Smuzhiyun /* our ALE is AD21 */ 53*4882a593Smuzhiyun #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) 54*4882a593Smuzhiyun /* our CLE is AD22 */ 55*4882a593Smuzhiyun #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) 56*4882a593Smuzhiyun #define CONFIG_SYS_NAND_ONFI_DETECTION 57*4882a593Smuzhiyun /* PMECC & PMERRLOC */ 58*4882a593Smuzhiyun #define CONFIG_ATMEL_NAND_HWECC 59*4882a593Smuzhiyun #define CONFIG_ATMEL_NAND_HW_PMECC 60*4882a593Smuzhiyun #endif 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun /* USB device */ 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /* Ethernet Hardware */ 65*4882a593Smuzhiyun #define CONFIG_MACB 66*4882a593Smuzhiyun #define CONFIG_RMII 67*4882a593Smuzhiyun #define CONFIG_NET_RETRY_COUNT 20 68*4882a593Smuzhiyun #define CONFIG_MACB_SEARCH_PHY 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun #ifdef CONFIG_SYS_USE_NANDFLASH 71*4882a593Smuzhiyun #undef CONFIG_ENV_OFFSET 72*4882a593Smuzhiyun #undef CONFIG_ENV_OFFSET_REDUND 73*4882a593Smuzhiyun #undef CONFIG_BOOTCOMMAND 74*4882a593Smuzhiyun /* u-boot env in nand flash */ 75*4882a593Smuzhiyun #define CONFIG_ENV_OFFSET 0x200000 76*4882a593Smuzhiyun #define CONFIG_ENV_OFFSET_REDUND 0x400000 77*4882a593Smuzhiyun #define CONFIG_BOOTCOMMAND "nand read 0x21000000 0xb80000 0x80000;" \ 78*4882a593Smuzhiyun "nand read 0x22000000 0x600000 0x600000;" \ 79*4882a593Smuzhiyun "bootz 0x22000000 - 0x21000000" 80*4882a593Smuzhiyun #endif 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /* SPL */ 83*4882a593Smuzhiyun #define CONFIG_SPL_FRAMEWORK 84*4882a593Smuzhiyun #define CONFIG_SPL_TEXT_BASE 0x200000 85*4882a593Smuzhiyun #define CONFIG_SPL_MAX_SIZE 0x10000 86*4882a593Smuzhiyun #define CONFIG_SPL_BSS_START_ADDR 0x20000000 87*4882a593Smuzhiyun #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 88*4882a593Smuzhiyun #define CONFIG_SYS_SPL_MALLOC_START 0x20080000 89*4882a593Smuzhiyun #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun #define CONFIG_SYS_MONITOR_LEN (512 << 10) 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun #ifdef CONFIG_SYS_USE_SERIALFLASH 94*4882a593Smuzhiyun #define CONFIG_SPL_SPI_LOAD 95*4882a593Smuzhiyun #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun #elif CONFIG_SYS_USE_NANDFLASH 98*4882a593Smuzhiyun #define CONFIG_SPL_NAND_DRIVERS 99*4882a593Smuzhiyun #define CONFIG_SPL_NAND_BASE 100*4882a593Smuzhiyun #define CONFIG_PMECC_CAP 8 101*4882a593Smuzhiyun #define CONFIG_PMECC_SECTOR_SIZE 512 102*4882a593Smuzhiyun #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 103*4882a593Smuzhiyun #define CONFIG_SYS_NAND_5_ADDR_CYCLE 104*4882a593Smuzhiyun #define CONFIG_SYS_NAND_PAGE_SIZE 0x1000 105*4882a593Smuzhiyun #define CONFIG_SYS_NAND_PAGE_COUNT 64 106*4882a593Smuzhiyun #define CONFIG_SYS_NAND_OOBSIZE 224 107*4882a593Smuzhiyun #define CONFIG_SYS_NAND_BLOCK_SIZE 0x40000 108*4882a593Smuzhiyun #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 109*4882a593Smuzhiyun #define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER 110*4882a593Smuzhiyun #endif 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun #endif 113