1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * include/configs/salvator-x.h 3*4882a593Smuzhiyun * This file is Salvator-X board configuration. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2015 Renesas Electronics Corporation 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __SALVATOR_X_H 11*4882a593Smuzhiyun #define __SALVATOR_X_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #undef DEBUG 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define CONFIG_RCAR_BOARD_STRING "Salvator-X" 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #include "rcar-gen3-common.h" 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* SCIF */ 20*4882a593Smuzhiyun #define CONFIG_CONS_SCIF2 21*4882a593Smuzhiyun #define CONFIG_CONS_INDEX 2 22*4882a593Smuzhiyun #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_S3D4_CLK_FREQ 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* [A] Hyper Flash */ 25*4882a593Smuzhiyun /* use to RPC(SPI Multi I/O Bus Controller) */ 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* Ethernet RAVB */ 28*4882a593Smuzhiyun #define CONFIG_NET_MULTI 29*4882a593Smuzhiyun #define CONFIG_BITBANGMII 30*4882a593Smuzhiyun #define CONFIG_BITBANGMII_MULTI 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* Board Clock */ 33*4882a593Smuzhiyun /* XTAL_CLK : 33.33MHz */ 34*4882a593Smuzhiyun #define RCAR_XTAL_CLK 33333333u 35*4882a593Smuzhiyun #define CONFIG_SYS_CLK_FREQ RCAR_XTAL_CLK 36*4882a593Smuzhiyun /* ch0to2 CPclk, ch3to11 S3D2_PEREclk, ch12to14 S3D2_RTclk */ 37*4882a593Smuzhiyun /* CPclk 16.66MHz, S3D2 133.33MHz , S3D4 66.66MHz */ 38*4882a593Smuzhiyun #define CONFIG_CP_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) 39*4882a593Smuzhiyun #define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 192 / 2) 40*4882a593Smuzhiyun #define CONFIG_S3D2_CLK_FREQ (266666666u/2) 41*4882a593Smuzhiyun #define CONFIG_S3D4_CLK_FREQ (266666666u/4) 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* Generic Timer Definitions (use in assembler source) */ 44*4882a593Smuzhiyun #define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */ 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* Generic Interrupt Controller Definitions */ 47*4882a593Smuzhiyun #define CONFIG_GICV2 48*4882a593Smuzhiyun #define GICD_BASE 0xF1010000 49*4882a593Smuzhiyun #define GICC_BASE 0xF1020000 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* i2c */ 52*4882a593Smuzhiyun #define CONFIG_SYS_I2C 53*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SH 54*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SLAVE 0x60 55*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 1 56*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SH_SPEED0 400000 57*4882a593Smuzhiyun #define CONFIG_SH_I2C_DATA_HIGH 4 58*4882a593Smuzhiyun #define CONFIG_SH_I2C_DATA_LOW 5 59*4882a593Smuzhiyun #define CONFIG_SH_I2C_CLOCK 10000000 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #define CONFIG_SYS_I2C_POWERIC_ADDR 0x30 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun /* USB */ 64*4882a593Smuzhiyun #ifdef CONFIG_R8A7795 65*4882a593Smuzhiyun #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 66*4882a593Smuzhiyun #else 67*4882a593Smuzhiyun #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 68*4882a593Smuzhiyun #endif 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun /* SDHI */ 71*4882a593Smuzhiyun #define CONFIG_SH_SDHI_FREQ 200000000 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun /* Environment in eMMC, at the end of 2nd "boot sector" */ 74*4882a593Smuzhiyun #define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) 75*4882a593Smuzhiyun #define CONFIG_SYS_MMC_ENV_DEV 1 76*4882a593Smuzhiyun #define CONFIG_SYS_MMC_ENV_PART 2 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun /* Module stop status bits */ 79*4882a593Smuzhiyun /* MFIS, SCIF1 */ 80*4882a593Smuzhiyun #define CONFIG_SMSTP2_ENA 0x00002040 81*4882a593Smuzhiyun /* SCIF2 */ 82*4882a593Smuzhiyun #define CONFIG_SMSTP3_ENA 0x00000400 83*4882a593Smuzhiyun /* INTC-AP, IRQC */ 84*4882a593Smuzhiyun #define CONFIG_SMSTP4_ENA 0x00000180 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun #endif /* __SALVATOR_X_H */ 87