1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2019 Rockchip Electronics Co., Ltd 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __CONFIG_RV1126_COMMON_H 8*4882a593Smuzhiyun #define __CONFIG_RV1126_COMMON_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include "rockchip-common.h" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define COUNTER_FREQUENCY 24000000 13*4882a593Smuzhiyun #define CONFIG_SYS_MALLOC_LEN (32 << 20) 14*4882a593Smuzhiyun #define CONFIG_SYS_CBSIZE 1024 15*4882a593Smuzhiyun #define CONFIG_SYS_NS16550_MEM32 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #ifdef CONFIG_SUPPORT_USBPLUG 18*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0x00000000 19*4882a593Smuzhiyun #else 20*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0x00600000 21*4882a593Smuzhiyun #endif 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_ADDR 0x00800000 24*4882a593Smuzhiyun #define CONFIG_SYS_LOAD_ADDR 0x00e00800 25*4882a593Smuzhiyun #define CONFIG_SYS_BOOTM_LEN (64 << 20) 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* SPL */ 28*4882a593Smuzhiyun #define CONFIG_SPL_FRAMEWORK 29*4882a593Smuzhiyun #define CONFIG_SPL_TEXT_BASE 0x00000000 30*4882a593Smuzhiyun #define CONFIG_SPL_MAX_SIZE 0x30000 31*4882a593Smuzhiyun #define CONFIG_SPL_BSS_START_ADDR 0x00600000 32*4882a593Smuzhiyun #define CONFIG_SPL_BSS_MAX_SIZE 0x20000 33*4882a593Smuzhiyun #define CONFIG_SPL_STACK 0x00600000 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define GICD_BASE 0xfeff1000 36*4882a593Smuzhiyun #define GICC_BASE 0xfeff2000 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* secure boot otp rollback */ 39*4882a593Smuzhiyun #define OTP_UBOOT_ROLLBACK_OFFSET 0x68 40*4882a593Smuzhiyun #define OTP_UBOOT_ROLLBACK_WORDS 2 /* 64 bits, 2 words */ 41*4882a593Smuzhiyun #define OTP_ALL_ONES_NUM_BITS 32 42*4882a593Smuzhiyun #define OTP_SECURE_BOOT_ENABLE_ADDR 0x0 43*4882a593Smuzhiyun #define OTP_SECURE_BOOT_ENABLE_SIZE 1 44*4882a593Smuzhiyun #define OTP_RSA_HASH_ADDR 0x10 45*4882a593Smuzhiyun #define OTP_RSA_HASH_SIZE 32 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* MMC/SD IP block */ 48*4882a593Smuzhiyun #define CONFIG_BOUNCE_BUFFER 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* Nand */ 51*4882a593Smuzhiyun #define CONFIG_SYS_MAX_NAND_DEVICE 1 52*4882a593Smuzhiyun #define CONFIG_SYS_NAND_ONFI_DETECTION 53*4882a593Smuzhiyun #define CONFIG_SYS_NAND_PAGE_SIZE 2048 54*4882a593Smuzhiyun #define CONFIG_SYS_NAND_PAGE_COUNT 64 55*4882a593Smuzhiyun #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) 56*4882a593Smuzhiyun #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x4000 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_BASE 0 59*4882a593Smuzhiyun #define SDRAM_MAX_SIZE 0xfd000000 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #define CONFIG_PERIPH_DEVICE_START_ADDR (CONFIG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE) 62*4882a593Smuzhiyun #define CONFIG_PERIPH_DEVICE_END_ADDR SZ_4G 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */ 65*4882a593Smuzhiyun #ifndef CONFIG_SPL_BUILD 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun /* usb mass storage */ 68*4882a593Smuzhiyun #define CONFIG_USB_FUNCTION_MASS_STORAGE 69*4882a593Smuzhiyun #define CONFIG_ROCKUSB_G_DNL_PID 0x110b 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* memory size <= 128MB, TEE: 0x3000000 - 0x3200000 */ 72*4882a593Smuzhiyun #define ENV_MEM_LAYOUT_SETTINGS1 \ 73*4882a593Smuzhiyun "scriptaddr1=0x00000000\0" \ 74*4882a593Smuzhiyun "pxefile_addr1_r=0x00100000\0" \ 75*4882a593Smuzhiyun "fdt_addr1_r=0x02f00000\0" \ 76*4882a593Smuzhiyun "kernel_addr1_r=0x02008000\0" \ 77*4882a593Smuzhiyun "ramdisk_addr1_r=0x03200000\0" 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun /* memory size > 128MB */ 80*4882a593Smuzhiyun #define ENV_MEM_LAYOUT_SETTINGS \ 81*4882a593Smuzhiyun "scriptaddr=0x00000000\0" \ 82*4882a593Smuzhiyun "pxefile_addr_r=0x00100000\0" \ 83*4882a593Smuzhiyun "fdt_addr_r=0x08300000\0" \ 84*4882a593Smuzhiyun "kernel_addr_r=0x02008000\0" \ 85*4882a593Smuzhiyun "ramdisk_addr_r=0x0a200000\0" 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun #include <config_distro_bootcmd.h> 88*4882a593Smuzhiyun #define CONFIG_EXTRA_ENV_SETTINGS \ 89*4882a593Smuzhiyun ENV_MEM_LAYOUT_SETTINGS \ 90*4882a593Smuzhiyun ENV_MEM_LAYOUT_SETTINGS1 \ 91*4882a593Smuzhiyun "partitions=" PARTS_DEFAULT \ 92*4882a593Smuzhiyun ROCKCHIP_DEVICE_SETTINGS \ 93*4882a593Smuzhiyun RKIMG_DET_BOOTDEV \ 94*4882a593Smuzhiyun BOOTENV_SHARED_RKNAND \ 95*4882a593Smuzhiyun BOOTENV 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun #undef RKIMG_BOOTCOMMAND 98*4882a593Smuzhiyun #ifdef CONFIG_FIT_SIGNATURE 99*4882a593Smuzhiyun #define RKIMG_BOOTCOMMAND \ 100*4882a593Smuzhiyun "boot_fit;" 101*4882a593Smuzhiyun #else 102*4882a593Smuzhiyun #define RKIMG_BOOTCOMMAND \ 103*4882a593Smuzhiyun "boot_fit;" \ 104*4882a593Smuzhiyun "boot_android ${devtype} ${devnum};" 105*4882a593Smuzhiyun #endif 106*4882a593Smuzhiyun #endif 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun #define CONFIG_LIB_HW_RAND 109*4882a593Smuzhiyun #define CONFIG_PREBOOT 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun #endif 112