1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Configuation settings for the Renesas RSK2+SH7264 board 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2011 Renesas Electronics Europe Ltd. 5*4882a593Smuzhiyun * Copyright (C) 2008 Nobuhiro Iwamatsu 6*4882a593Smuzhiyun * Copyright (C) 2008 Renesas Solutions Corp. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef __RSK7264_H 12*4882a593Smuzhiyun #define __RSK7264_H 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define CONFIG_CPU_SH7264 1 15*4882a593Smuzhiyun #define CONFIG_RSK7264 1 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define CONFIG_DISPLAY_BOARDINFO 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE } 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define CONFIG_SYS_LONGHELP 1 /* undef to save memory */ 22*4882a593Smuzhiyun #define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */ 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* Serial */ 25*4882a593Smuzhiyun #define CONFIG_CONS_SCIF3 1 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* Memory */ 28*4882a593Smuzhiyun /* u-boot relocated to top 256KB of ram */ 29*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0x0CFC0000 30*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_BASE 0x0C000000 31*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 34*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000) 35*4882a593Smuzhiyun #define CONFIG_SYS_MALLOC_LEN (256 * 1024) 36*4882a593Smuzhiyun #define CONFIG_SYS_MONITOR_LEN (128 * 1024) 37*4882a593Smuzhiyun #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4*1024*1024) 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* Flash */ 40*4882a593Smuzhiyun #define CONFIG_FLASH_CFI_DRIVER 41*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_CFI 42*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 43*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_BASE 0x20000000 /* Non-cached */ 44*4882a593Smuzhiyun #define CONFIG_SYS_MAX_FLASH_BANKS 1 45*4882a593Smuzhiyun #define CONFIG_SYS_MAX_FLASH_SECT 512 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define CONFIG_ENV_OFFSET (128 * 1024) 48*4882a593Smuzhiyun #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) 49*4882a593Smuzhiyun #define CONFIG_ENV_SECT_SIZE (128 * 1024) 50*4882a593Smuzhiyun #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* Board Clock */ 53*4882a593Smuzhiyun #define CONFIG_SYS_CLK_FREQ 36000000 54*4882a593Smuzhiyun #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ 55*4882a593Smuzhiyun #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 56*4882a593Smuzhiyun #define CMT_CLK_DIVIDER 32 /* 8 (default), 32, 128 or 512 */ 57*4882a593Smuzhiyun #define CONFIG_SH_CMT_CLK_FREQ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER) 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* Network interface */ 60*4882a593Smuzhiyun #define CONFIG_SMC911X 61*4882a593Smuzhiyun #define CONFIG_SMC911X_16_BIT 62*4882a593Smuzhiyun #define CONFIG_SMC911X_BASE 0x28000000 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #endif /* __RSK7264_H */ 65