1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Configuation settings for the Renesas Technology RSK 7203 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2008 Nobuhiro Iwamatsu 5*4882a593Smuzhiyun * Copyright (C) 2008 Renesas Solutions Corp. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __RSK7203_H 11*4882a593Smuzhiyun #define __RSK7203_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define CONFIG_CPU_SH7203 1 14*4882a593Smuzhiyun #define CONFIG_RSK7203 1 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define CONFIG_LOADADDR 0x0C100000 /* RSK7203_SDRAM_BASE + 1MB */ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define CONFIG_DISPLAY_BOARDINFO 19*4882a593Smuzhiyun #undef CONFIG_SHOW_BOOT_PROGRESS 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* MEMORY */ 22*4882a593Smuzhiyun #define RSK7203_SDRAM_BASE 0x0C000000 23*4882a593Smuzhiyun #define RSK7203_FLASH_BASE_1 0x20000000 /* Non cache */ 24*4882a593Smuzhiyun #define RSK7203_FLASH_BANK_SIZE (4 * 1024 * 1024) 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0x0C7C0000 27*4882a593Smuzhiyun #define CONFIG_SYS_LONGHELP /* undef to save memory */ 28*4882a593Smuzhiyun /* List of legal baudrate settings for this board */ 29*4882a593Smuzhiyun #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* SCIF */ 32*4882a593Smuzhiyun #define CONFIG_CONS_SCIF0 1 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_START RSK7203_SDRAM_BASE 35*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (3 * 1024 * 1024)) 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_BASE RSK7203_SDRAM_BASE 38*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_SIZE (32 * 1024 * 1024) 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 1024 * 1024) 41*4882a593Smuzhiyun #define CONFIG_SYS_MONITOR_BASE RSK7203_FLASH_BASE_1 42*4882a593Smuzhiyun #define CONFIG_SYS_MONITOR_LEN (128 * 1024) 43*4882a593Smuzhiyun #define CONFIG_SYS_MALLOC_LEN (256 * 1024) 44*4882a593Smuzhiyun #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* FLASH */ 47*4882a593Smuzhiyun #define CONFIG_FLASH_CFI_DRIVER 48*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_CFI 49*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 50*4882a593Smuzhiyun #undef CONFIG_SYS_FLASH_QUIET_TEST 51*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ 52*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_BASE RSK7203_FLASH_BASE_1 53*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 54*4882a593Smuzhiyun #define CONFIG_SYS_MAX_FLASH_SECT 64 55*4882a593Smuzhiyun #define CONFIG_SYS_MAX_FLASH_BANKS 1 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #define CONFIG_ENV_SECT_SIZE (64 * 1024) 58*4882a593Smuzhiyun #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 59*4882a593Smuzhiyun #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 60*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_ERASE_TOUT 12000 61*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_WRITE_TOUT 500 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun /* Board Clock */ 64*4882a593Smuzhiyun #define CONFIG_SYS_CLK_FREQ 33333333 65*4882a593Smuzhiyun #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ 66*4882a593Smuzhiyun #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 67*4882a593Smuzhiyun #define CMT_CLK_DIVIDER 32 /* 8 (default), 32, 128 or 512 */ 68*4882a593Smuzhiyun #define CONFIG_SH_CMT_CLK_FREQ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER) 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun /* Network interface */ 71*4882a593Smuzhiyun #define CONFIG_SMC911X 72*4882a593Smuzhiyun #define CONFIG_SMC911X_16_BIT 73*4882a593Smuzhiyun #define CONFIG_SMC911X_BASE (0x24000000) 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun #endif /* __RSK7203_H */ 76