1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * (C) Copyright 2020 Rockchip Electronics Co., Ltd 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __CONFIG_RK3568_COMMON_H 8*4882a593Smuzhiyun #define __CONFIG_RK3568_COMMON_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include "rockchip-common.h" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define CONFIG_SPL_FRAMEWORK 13*4882a593Smuzhiyun #define CONFIG_SPL_TEXT_BASE 0x00000000 14*4882a593Smuzhiyun #define CONFIG_SPL_MAX_SIZE 0x00040000 15*4882a593Smuzhiyun #define CONFIG_SPL_BSS_START_ADDR 0x03fe0000 16*4882a593Smuzhiyun #define CONFIG_SPL_BSS_MAX_SIZE 0x00010000 17*4882a593Smuzhiyun #define CONFIG_SPL_STACK 0x03fe0000 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define CONFIG_SYS_MALLOC_LEN (32 << 20) 20*4882a593Smuzhiyun #define CONFIG_SYS_CBSIZE 1024 21*4882a593Smuzhiyun #define CONFIG_SKIP_LOWLEVEL_INIT 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #ifdef CONFIG_SUPPORT_USBPLUG 24*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0x00000000 25*4882a593Smuzhiyun #else 26*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0x00a00000 27*4882a593Smuzhiyun #endif 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_ADDR 0x00c00000 30*4882a593Smuzhiyun #define CONFIG_SYS_LOAD_ADDR 0x00c00800 31*4882a593Smuzhiyun #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ 32*4882a593Smuzhiyun #define COUNTER_FREQUENCY 24000000 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define GICD_BASE 0xfd400000 35*4882a593Smuzhiyun #define GICR_BASE 0xfd460000 36*4882a593Smuzhiyun #define GICC_BASE 0xfd800000 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* secure otp */ 39*4882a593Smuzhiyun #define OTP_UBOOT_ROLLBACK_OFFSET 0xe0 40*4882a593Smuzhiyun #define OTP_UBOOT_ROLLBACK_WORDS 2 /* 64 bits, 2 words */ 41*4882a593Smuzhiyun #define OTP_ALL_ONES_NUM_BITS 32 42*4882a593Smuzhiyun #define OTP_SECURE_BOOT_ENABLE_ADDR 0x80 43*4882a593Smuzhiyun #define OTP_SECURE_BOOT_ENABLE_SIZE 2 44*4882a593Smuzhiyun #define OTP_RSA_HASH_ADDR 0x90 45*4882a593Smuzhiyun #define OTP_RSA_HASH_SIZE 32 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* MMC/SD IP block */ 48*4882a593Smuzhiyun #define CONFIG_BOUNCE_BUFFER 49*4882a593Smuzhiyun #ifdef CONFIG_AHCI 50*4882a593Smuzhiyun #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 51*4882a593Smuzhiyun #define CONFIG_SYS_SCSI_MAX_LUN 1 52*4882a593Smuzhiyun /*#define CONFIG_SCSI_AHCI_PLAT */ 53*4882a593Smuzhiyun #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 54*4882a593Smuzhiyun CONFIG_SYS_SCSI_MAX_LUN) 55*4882a593Smuzhiyun #endif 56*4882a593Smuzhiyun /* Nand */ 57*4882a593Smuzhiyun #define CONFIG_SYS_MAX_NAND_DEVICE 1 58*4882a593Smuzhiyun #define CONFIG_SYS_NAND_ONFI_DETECTION 59*4882a593Smuzhiyun #define CONFIG_SYS_NAND_PAGE_SIZE 2048 60*4882a593Smuzhiyun #define CONFIG_SYS_NAND_PAGE_COUNT 64 61*4882a593Smuzhiyun #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_BASE 0 64*4882a593Smuzhiyun #define SDRAM_MAX_SIZE 0xf0000000 65*4882a593Smuzhiyun #define CONFIG_PREBOOT 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */ 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #ifndef CONFIG_SPL_BUILD 70*4882a593Smuzhiyun /* usb mass storage */ 71*4882a593Smuzhiyun #define CONFIG_USB_FUNCTION_MASS_STORAGE 72*4882a593Smuzhiyun #define CONFIG_ROCKUSB_G_DNL_PID 0x350a 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun #define ENV_MEM_LAYOUT_SETTINGS \ 75*4882a593Smuzhiyun "scriptaddr=0x00c00000\0" \ 76*4882a593Smuzhiyun "pxefile_addr_r=0x00e00000\0" \ 77*4882a593Smuzhiyun "fdt_addr_r=0x08300000\0" \ 78*4882a593Smuzhiyun "kernel_addr_r=0x00280000\0" \ 79*4882a593Smuzhiyun "kernel_addr_c=0x04080000\0" \ 80*4882a593Smuzhiyun "ramdisk_addr_r=0x0a200000\0" 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun #include <config_distro_bootcmd.h> 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun #define CONFIG_EXTRA_ENV_SETTINGS \ 85*4882a593Smuzhiyun ENV_MEM_LAYOUT_SETTINGS \ 86*4882a593Smuzhiyun "partitions=" PARTS_RKIMG \ 87*4882a593Smuzhiyun ROCKCHIP_DEVICE_SETTINGS \ 88*4882a593Smuzhiyun RKIMG_DET_BOOTDEV \ 89*4882a593Smuzhiyun BOOTENV 90*4882a593Smuzhiyun #endif 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun /* rockchip ohci host driver */ 93*4882a593Smuzhiyun #define CONFIG_USB_OHCI_NEW 94*4882a593Smuzhiyun #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun #define CONFIG_LIB_HW_RAND 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun #endif 99