1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * (C) Copyright 2022 Rockchip Electronics Co., Ltd 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __CONFIG_RK3562_COMMON_H 8*4882a593Smuzhiyun #define __CONFIG_RK3562_COMMON_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include "rockchip-common.h" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define CONFIG_SPL_FRAMEWORK 13*4882a593Smuzhiyun #define CONFIG_SPL_TEXT_BASE 0x00000000 14*4882a593Smuzhiyun #define CONFIG_SPL_MAX_SIZE 0x00040000 15*4882a593Smuzhiyun #define CONFIG_SPL_BSS_START_ADDR 0x03fe0000 16*4882a593Smuzhiyun #define CONFIG_SPL_BSS_MAX_SIZE 0x00010000 17*4882a593Smuzhiyun #define CONFIG_SPL_STACK 0x03fe0000 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define CONFIG_SYS_MALLOC_LEN (32 << 20) 20*4882a593Smuzhiyun #define CONFIG_SYS_CBSIZE 1024 21*4882a593Smuzhiyun #define CONFIG_SKIP_LOWLEVEL_INIT 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #ifdef CONFIG_SUPPORT_USBPLUG 24*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0x00000000 25*4882a593Smuzhiyun #else 26*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0x00200000 27*4882a593Smuzhiyun #endif 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_ADDR 0x00c00000 30*4882a593Smuzhiyun #define CONFIG_SYS_LOAD_ADDR 0x00c00800 31*4882a593Smuzhiyun #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ 32*4882a593Smuzhiyun #define COUNTER_FREQUENCY 24000000 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define GICD_BASE 0xfe901000 35*4882a593Smuzhiyun #define GICC_BASE 0xfe902000 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* secure otp */ 38*4882a593Smuzhiyun #define OTP_UBOOT_ROLLBACK_OFFSET 0x350 39*4882a593Smuzhiyun #define OTP_UBOOT_ROLLBACK_WORDS 2 /* 64 bits, 2 words */ 40*4882a593Smuzhiyun #define OTP_ALL_ONES_NUM_BITS 32 41*4882a593Smuzhiyun #define OTP_SECURE_BOOT_ENABLE_ADDR 0x20 42*4882a593Smuzhiyun #define OTP_SECURE_BOOT_ENABLE_SIZE 1 43*4882a593Smuzhiyun #define OTP_RSA_HASH_ADDR 0x180 44*4882a593Smuzhiyun #define OTP_RSA_HASH_SIZE 32 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* MMC/SD IP block */ 47*4882a593Smuzhiyun #define CONFIG_BOUNCE_BUFFER 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_BASE 0 50*4882a593Smuzhiyun #define SDRAM_MAX_SIZE 0xfc000000 51*4882a593Smuzhiyun #define CONFIG_PREBOOT 52*4882a593Smuzhiyun #define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */ 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #define CONFIG_SPL_LOAD_FIT_ADDRESS 0x2000000 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #ifndef CONFIG_SPL_BUILD 57*4882a593Smuzhiyun /* usb mass storage */ 58*4882a593Smuzhiyun #define CONFIG_USB_FUNCTION_MASS_STORAGE 59*4882a593Smuzhiyun #define CONFIG_ROCKUSB_G_DNL_PID 0x350d 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #define ENV_MEM_LAYOUT_SETTINGS \ 62*4882a593Smuzhiyun "scriptaddr=0x00c00000\0" \ 63*4882a593Smuzhiyun "pxefile_addr_r=0x00e00000\0" \ 64*4882a593Smuzhiyun "fdt_addr_r=0x08300000\0" \ 65*4882a593Smuzhiyun "kernel_addr_r=0x00400000\0" \ 66*4882a593Smuzhiyun "kernel_addr_c=0x04080000\0" \ 67*4882a593Smuzhiyun "ramdisk_addr_r=0x0a200000\0" 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #include <config_distro_bootcmd.h> 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun #define CONFIG_EXTRA_ENV_SETTINGS \ 72*4882a593Smuzhiyun ENV_MEM_LAYOUT_SETTINGS \ 73*4882a593Smuzhiyun "partitions=" PARTS_RKIMG \ 74*4882a593Smuzhiyun ROCKCHIP_DEVICE_SETTINGS \ 75*4882a593Smuzhiyun RKIMG_DET_BOOTDEV \ 76*4882a593Smuzhiyun BOOTENV 77*4882a593Smuzhiyun #endif 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun /* rockchip ohci host driver */ 80*4882a593Smuzhiyun #define CONFIG_USB_OHCI_NEW 81*4882a593Smuzhiyun #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 82*4882a593Smuzhiyun #define CONFIG_LIB_HW_RAND 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun #endif 85