1 /* 2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_RK3308_COMMON_H 8 #define __CONFIG_RK3308_COMMON_H 9 10 #include "rockchip-common.h" 11 12 #define CONFIG_SYS_MALLOC_LEN (10 << 20) 13 #define CONFIG_SYS_CBSIZE 1024 14 #define CONFIG_SKIP_LOWLEVEL_INIT 15 #define CONFIG_SYS_MAX_NAND_DEVICE 1 16 #define CONFIG_SYS_NAND_ONFI_DETECTION 17 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 18 #define CONFIG_SYS_NAND_PAGE_COUNT 64 19 #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) 20 #define CONFIG_SPL_FRAMEWORK 21 #define CONFIG_SPL_TEXT_BASE 0x00000000 22 #define CONFIG_SPL_MAX_SIZE 0x40000 23 #define CONFIG_SPL_BSS_START_ADDR 0x00400000 24 #define CONFIG_SPL_BSS_MAX_SIZE 0x2000 25 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000 26 27 #define CONFIG_SYS_NS16550_MEM32 28 29 #define CONFIG_SYS_TEXT_BASE 0x00600000 30 #define CONFIG_SYS_INIT_SP_ADDR 0x00800000 31 #define CONFIG_SYS_LOAD_ADDR 0x00C00800 32 #define CONFIG_SPL_STACK 0x00400000 33 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ 34 35 #define COUNTER_FREQUENCY 24000000 36 37 #define GICD_BASE 0xff581000 38 #define GICC_BASE 0xff582000 39 40 #define OTP_SECURE_BOOT_ENABLE_ADDR 0x0 41 #define OTP_SECURE_BOOT_ENABLE_SIZE 1 42 #define OTP_RSA_HASH_ADDR 0x10 43 #define OTP_RSA_HASH_SIZE 32 44 45 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ 46 47 /* MMC/SD IP block */ 48 #define CONFIG_BOUNCE_BUFFER 49 50 #define CONFIG_SYS_SDRAM_BASE 0 51 #define SDRAM_MAX_SIZE 0xff000000 52 #define SDRAM_BANK_SIZE (2UL << 30) 53 #ifdef CONFIG_DM_DVFS 54 #define CONFIG_PREBOOT "dvfs repeat" 55 #else 56 #define CONFIG_PREBOOT 57 #endif 58 59 #ifndef CONFIG_SPL_BUILD 60 61 /* usb mass storage */ 62 #define CONFIG_USB_FUNCTION_MASS_STORAGE 63 #define CONFIG_ROCKUSB_G_DNL_PID 0x330d 64 65 #ifdef CONFIG_ARM64 66 #define ENV_MEM_LAYOUT_SETTINGS \ 67 "scriptaddr=0x00500000\0" \ 68 "pxefile_addr_r=0x00600000\0" \ 69 "fdt_addr_r=0x01f00000\0" \ 70 "kernel_addr_no_low_bl32_r=0x00280000\0" \ 71 "kernel_addr_r=0x00680000\0" \ 72 "kernel_addr_c=0x02480000\0" \ 73 "ramdisk_addr_r=0x04000000\0" 74 #else 75 #define ENV_MEM_LAYOUT_SETTINGS \ 76 "scriptaddr=0x00500000\0" \ 77 "pxefile_addr_r=0x00600000\0" \ 78 "fdt_addr_r=0x02800000\0" \ 79 "kernel_addr_r=0x00058000\0" \ 80 "kernel_addr_c=0x2008000\0" \ 81 "ramdisk_addr_r=0x02900000\0" 82 #endif 83 84 #include <config_distro_bootcmd.h> 85 #define CONFIG_EXTRA_ENV_SETTINGS \ 86 ENV_MEM_LAYOUT_SETTINGS \ 87 "partitions=" PARTS_DEFAULT \ 88 ROCKCHIP_DEVICE_SETTINGS \ 89 RKIMG_DET_BOOTDEV \ 90 BOOTENV_SHARED_RKNAND \ 91 BOOTENV 92 93 #endif 94 95 #endif 96