1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Configuation settings for the Renesas R7780MP board 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> 5*4882a593Smuzhiyun * Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __R7780RP_H 11*4882a593Smuzhiyun #define __R7780RP_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define CONFIG_CPU_SH7780 1 14*4882a593Smuzhiyun #define CONFIG_R7780MP 1 15*4882a593Smuzhiyun #define CONFIG_SYS_R7780MP_OLD_FLASH 1 16*4882a593Smuzhiyun #define __LITTLE_ENDIAN__ 1 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define CONFIG_DISPLAY_BOARDINFO 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define CONFIG_CONS_SCIF0 1 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define CONFIG_ENV_OVERWRITE 1 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0x0FFC0000 25*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_BASE (0x08000000) 26*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024) 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define CONFIG_SYS_LONGHELP 29*4882a593Smuzhiyun #define CONFIG_SYS_PBSIZE 256 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE) 32*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000) 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* Flash board support */ 35*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_BASE (0xA0000000) 36*4882a593Smuzhiyun #ifdef CONFIG_SYS_R7780MP_OLD_FLASH 37*4882a593Smuzhiyun /* NOR Flash (S29PL127J60TFI130) */ 38*4882a593Smuzhiyun # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT 39*4882a593Smuzhiyun # define CONFIG_SYS_MAX_FLASH_BANKS (2) 40*4882a593Smuzhiyun # define CONFIG_SYS_MAX_FLASH_SECT 270 41*4882a593Smuzhiyun # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ 42*4882a593Smuzhiyun CONFIG_SYS_FLASH_BASE + 0x100000,\ 43*4882a593Smuzhiyun CONFIG_SYS_FLASH_BASE + 0x400000,\ 44*4882a593Smuzhiyun CONFIG_SYS_FLASH_BASE + 0x700000, } 45*4882a593Smuzhiyun #else /* CONFIG_SYS_R7780MP_OLD_FLASH */ 46*4882a593Smuzhiyun /* NOR Flash (Spantion S29GL256P) */ 47*4882a593Smuzhiyun # define CONFIG_SYS_MAX_FLASH_BANKS (1) 48*4882a593Smuzhiyun # define CONFIG_SYS_MAX_FLASH_SECT 256 49*4882a593Smuzhiyun # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 50*4882a593Smuzhiyun #endif /* CONFIG_SYS_R7780MP_OLD_FLASH */ 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024) 53*4882a593Smuzhiyun /* Address of u-boot image in Flash */ 54*4882a593Smuzhiyun #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) 55*4882a593Smuzhiyun #define CONFIG_SYS_MONITOR_LEN (256 * 1024) 56*4882a593Smuzhiyun /* Size of DRAM reserved for malloc() use */ 57*4882a593Smuzhiyun #define CONFIG_SYS_MALLOC_LEN (1204 * 1024) 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 60*4882a593Smuzhiyun #define CONFIG_SYS_RX_ETH_BUFFER (8) 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_CFI 63*4882a593Smuzhiyun #define CONFIG_FLASH_CFI_DRIVER 64*4882a593Smuzhiyun #undef CONFIG_SYS_FLASH_CFI_BROKEN_TABLE 65*4882a593Smuzhiyun #undef CONFIG_SYS_FLASH_QUIET_TEST 66*4882a593Smuzhiyun /* print 'E' for empty sector on flinfo */ 67*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_EMPTY_INFO 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #define CONFIG_ENV_SECT_SIZE (256 * 1024) 70*4882a593Smuzhiyun #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 71*4882a593Smuzhiyun #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 72*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 73*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_WRITE_TOUT 500 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun /* Board Clock */ 76*4882a593Smuzhiyun #define CONFIG_SYS_CLK_FREQ 33333333 77*4882a593Smuzhiyun #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ 78*4882a593Smuzhiyun #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 79*4882a593Smuzhiyun #define CONFIG_SYS_TMU_CLK_DIV 4 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun /* PCI Controller */ 82*4882a593Smuzhiyun #if defined(CONFIG_CMD_PCI) 83*4882a593Smuzhiyun #define CONFIG_SH4_PCI 84*4882a593Smuzhiyun #define CONFIG_SH7780_PCI 85*4882a593Smuzhiyun #define CONFIG_SH7780_PCI_LSR 0x07f00001 86*4882a593Smuzhiyun #define CONFIG_SH7780_PCI_LAR CONFIG_SYS_SDRAM_SIZE 87*4882a593Smuzhiyun #define CONFIG_SH7780_PCI_BAR CONFIG_SYS_SDRAM_SIZE 88*4882a593Smuzhiyun #define CONFIG_PCI_SCAN_SHOW 1 89*4882a593Smuzhiyun #define __mem_pci 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun #define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */ 92*4882a593Smuzhiyun #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS 93*4882a593Smuzhiyun #define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */ 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun #define CONFIG_PCI_IO_BUS 0xFE200000 /* IO space base address */ 96*4882a593Smuzhiyun #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS 97*4882a593Smuzhiyun #define CONFIG_PCI_IO_SIZE 0x00200000 /* Size of IO window */ 98*4882a593Smuzhiyun #define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE 99*4882a593Smuzhiyun #define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE 100*4882a593Smuzhiyun #define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE 101*4882a593Smuzhiyun #endif /* CONFIG_CMD_PCI */ 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun #if defined(CONFIG_CMD_NET) 104*4882a593Smuzhiyun /* AX88796L Support(NE2000 base chip) */ 105*4882a593Smuzhiyun #define CONFIG_DRIVER_AX88796L 106*4882a593Smuzhiyun #define CONFIG_DRIVER_NE2000_BASE 0xA4100000 107*4882a593Smuzhiyun #endif 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun /* Compact flash Support */ 110*4882a593Smuzhiyun #if defined(CONFIG_IDE) 111*4882a593Smuzhiyun #define CONFIG_IDE_RESET 1 112*4882a593Smuzhiyun #define CONFIG_SYS_PIO_MODE 1 113*4882a593Smuzhiyun #define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */ 114*4882a593Smuzhiyun #define CONFIG_SYS_IDE_MAXDEVICE 1 115*4882a593Smuzhiyun #define CONFIG_SYS_ATA_BASE_ADDR 0xb4000000 116*4882a593Smuzhiyun #define CONFIG_SYS_ATA_STRIDE 2 /* 1bit shift */ 117*4882a593Smuzhiyun #define CONFIG_SYS_ATA_DATA_OFFSET 0x1000 /* data reg offset */ 118*4882a593Smuzhiyun #define CONFIG_SYS_ATA_REG_OFFSET 0x1000 /* reg offset */ 119*4882a593Smuzhiyun #define CONFIG_SYS_ATA_ALT_OFFSET 0x800 /* alternate register offset */ 120*4882a593Smuzhiyun #define CONFIG_IDE_SWAP_IO 121*4882a593Smuzhiyun #endif /* CONFIG_IDE */ 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun #endif /* __R7780RP_H */ 124