1*4882a593Smuzhiyun #ifndef __CONFIG_H 2*4882a593Smuzhiyun #define __CONFIG_H 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #define CONFIG_CPU_SH7751 1 5*4882a593Smuzhiyun #define CONFIG_CPU_SH_TYPE_R 1 6*4882a593Smuzhiyun #define CONFIG_R2DPLUS 1 7*4882a593Smuzhiyun #define __LITTLE_ENDIAN__ 1 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define CONFIG_DISPLAY_BOARDINFO 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* SCIF */ 12*4882a593Smuzhiyun #define CONFIG_CONS_SCIF1 1 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define CONFIG_ENV_OVERWRITE 1 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* SDRAM */ 17*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_BASE 0x8C000000 18*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_SIZE 0x04000000 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0x8FE00000 21*4882a593Smuzhiyun #define CONFIG_SYS_LONGHELP 22*4882a593Smuzhiyun #define CONFIG_SYS_PBSIZE 256 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE) 25*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000) 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024) 28*4882a593Smuzhiyun /* Address of u-boot image in Flash */ 29*4882a593Smuzhiyun #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) 30*4882a593Smuzhiyun #define CONFIG_SYS_MONITOR_LEN (256 * 1024) 31*4882a593Smuzhiyun /* Size of DRAM reserved for malloc() use */ 32*4882a593Smuzhiyun #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) 33*4882a593Smuzhiyun #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* 36*4882a593Smuzhiyun * NOR Flash ( Spantion S29GL256P ) 37*4882a593Smuzhiyun */ 38*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_CFI 39*4882a593Smuzhiyun #define CONFIG_FLASH_CFI_DRIVER 40*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_BASE (0xA0000000) 41*4882a593Smuzhiyun #define CONFIG_SYS_MAX_FLASH_BANKS (1) 42*4882a593Smuzhiyun #define CONFIG_SYS_MAX_FLASH_SECT 256 43*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define CONFIG_ENV_SECT_SIZE 0x40000 46*4882a593Smuzhiyun #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 47*4882a593Smuzhiyun #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* 50*4882a593Smuzhiyun * SuperH Clock setting 51*4882a593Smuzhiyun */ 52*4882a593Smuzhiyun #define CONFIG_SYS_CLK_FREQ 60000000 53*4882a593Smuzhiyun #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ 54*4882a593Smuzhiyun #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 55*4882a593Smuzhiyun #define CONFIG_SYS_TMU_CLK_DIV 4 56*4882a593Smuzhiyun #define CONFIG_SYS_PLL_SETTLING_TIME 100/* in us */ 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* 59*4882a593Smuzhiyun * IDE support 60*4882a593Smuzhiyun */ 61*4882a593Smuzhiyun #define CONFIG_IDE_RESET 1 62*4882a593Smuzhiyun #define CONFIG_SYS_PIO_MODE 1 63*4882a593Smuzhiyun #define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */ 64*4882a593Smuzhiyun #define CONFIG_SYS_IDE_MAXDEVICE 1 65*4882a593Smuzhiyun #define CONFIG_SYS_ATA_BASE_ADDR 0xb4000000 66*4882a593Smuzhiyun #define CONFIG_SYS_ATA_STRIDE 2 /* 1bit shift */ 67*4882a593Smuzhiyun #define CONFIG_SYS_ATA_DATA_OFFSET 0x1000 /* data reg offset */ 68*4882a593Smuzhiyun #define CONFIG_SYS_ATA_REG_OFFSET 0x1000 /* reg offset */ 69*4882a593Smuzhiyun #define CONFIG_SYS_ATA_ALT_OFFSET 0x800 /* alternate register offset */ 70*4882a593Smuzhiyun #define CONFIG_IDE_SWAP_IO 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* 73*4882a593Smuzhiyun * SuperH PCI Bridge Configration 74*4882a593Smuzhiyun */ 75*4882a593Smuzhiyun #define CONFIG_SH4_PCI 76*4882a593Smuzhiyun #define CONFIG_SH7751_PCI 77*4882a593Smuzhiyun #define CONFIG_PCI_SCAN_SHOW 1 78*4882a593Smuzhiyun #define __mem_pci 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun #define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */ 81*4882a593Smuzhiyun #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS 82*4882a593Smuzhiyun #define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */ 83*4882a593Smuzhiyun #define CONFIG_PCI_IO_BUS 0xFE240000 /* IO space base address */ 84*4882a593Smuzhiyun #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS 85*4882a593Smuzhiyun #define CONFIG_PCI_IO_SIZE 0x00040000 /* Size of IO window */ 86*4882a593Smuzhiyun #define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE 87*4882a593Smuzhiyun #define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE 88*4882a593Smuzhiyun #define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun #endif /* __CONFIG_H */ 91