1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Configuation settings for the Renesas Solutions r0p7734 board 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2010, 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __R0P7734_H 10*4882a593Smuzhiyun #define __R0P7734_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define CONFIG_CPU_SH7734 1 13*4882a593Smuzhiyun #define CONFIG_R0P7734 1 14*4882a593Smuzhiyun #define CONFIG_400MHZ_MODE 1 15*4882a593Smuzhiyun /* #define CONFIG_533MHZ_MODE 1 */ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0x8FFC0000 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define CONFIG_DISPLAY_BOARDINFO 20*4882a593Smuzhiyun #undef CONFIG_SHOW_BOOT_PROGRESS 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* Ether */ 23*4882a593Smuzhiyun #define CONFIG_SH_ETHER 1 24*4882a593Smuzhiyun #define CONFIG_SH_ETHER_USE_PORT (0) 25*4882a593Smuzhiyun #define CONFIG_SH_ETHER_PHY_ADDR (0x0) 26*4882a593Smuzhiyun #define CONFIG_PHY_SMSC 1 27*4882a593Smuzhiyun #define CONFIG_BITBANGMII 28*4882a593Smuzhiyun #define CONFIG_BITBANGMII_MULTI 29*4882a593Smuzhiyun #define CONFIG_SH_ETHER_SH7734_MII (0x00) /* MII */ 30*4882a593Smuzhiyun #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII 31*4882a593Smuzhiyun #ifndef CONFIG_SH_ETHER 32*4882a593Smuzhiyun # define CONFIG_SMC911X 33*4882a593Smuzhiyun # define CONFIG_SMC911X_16_BIT 34*4882a593Smuzhiyun # define CONFIG_SMC911X_BASE (0x84000000) 35*4882a593Smuzhiyun #endif 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* undef to save memory */ 38*4882a593Smuzhiyun #define CONFIG_SYS_LONGHELP 39*4882a593Smuzhiyun /* List of legal baudrate settings for this board */ 40*4882a593Smuzhiyun #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* SCIF */ 43*4882a593Smuzhiyun #define CONFIG_SCIF 1 44*4882a593Smuzhiyun #define CONFIG_CONS_SCIF3 1 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* Suppress display of console information at boot */ 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* SDRAM */ 49*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_BASE (0x88000000) 50*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024) 51*4882a593Smuzhiyun #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024) 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE) 54*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 100 * 1024 * 1024) 55*4882a593Smuzhiyun /* Enable alternate, more extensive, memory test */ 56*4882a593Smuzhiyun #undef CONFIG_SYS_ALT_MEMTEST 57*4882a593Smuzhiyun /* Scratch address used by the alternate memory test */ 58*4882a593Smuzhiyun #undef CONFIG_SYS_MEMTEST_SCRATCH 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /* Enable temporary baudrate change while serial download */ 61*4882a593Smuzhiyun #undef CONFIG_SYS_LOADS_BAUD_CHANGE 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun /* FLASH */ 64*4882a593Smuzhiyun #define CONFIG_FLASH_CFI_DRIVER 1 65*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_CFI 66*4882a593Smuzhiyun #undef CONFIG_SYS_FLASH_QUIET_TEST 67*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_EMPTY_INFO 68*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_BASE (0xA0000000) 69*4882a593Smuzhiyun #define CONFIG_SYS_MAX_FLASH_SECT 512 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* if you use all NOR Flash , you change dip-switch. Please see Manual. */ 72*4882a593Smuzhiyun #define CONFIG_SYS_MAX_FLASH_BANKS 1 73*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun /* Timeout for Flash erase operations (in ms) */ 76*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) 77*4882a593Smuzhiyun /* Timeout for Flash write operations (in ms) */ 78*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) 79*4882a593Smuzhiyun /* Timeout for Flash set sector lock bit operations (in ms) */ 80*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) 81*4882a593Smuzhiyun /* Timeout for Flash clear lock bit operations (in ms) */ 82*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun /* 85*4882a593Smuzhiyun * Use hardware flash sectors protection instead 86*4882a593Smuzhiyun * of U-Boot software protection 87*4882a593Smuzhiyun */ 88*4882a593Smuzhiyun #undef CONFIG_SYS_FLASH_PROTECTION 89*4882a593Smuzhiyun #undef CONFIG_SYS_DIRECT_FLASH_TFTP 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun /* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */ 92*4882a593Smuzhiyun #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) 93*4882a593Smuzhiyun /* Monitor size */ 94*4882a593Smuzhiyun #define CONFIG_SYS_MONITOR_LEN (256 * 1024) 95*4882a593Smuzhiyun /* Size of DRAM reserved for malloc() use */ 96*4882a593Smuzhiyun #define CONFIG_SYS_MALLOC_LEN (256 * 1024) 97*4882a593Smuzhiyun #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun /* ENV setting */ 100*4882a593Smuzhiyun #define CONFIG_ENV_OVERWRITE 1 101*4882a593Smuzhiyun #define CONFIG_ENV_SECT_SIZE (128 * 1024) 102*4882a593Smuzhiyun #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 103*4882a593Smuzhiyun #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) 104*4882a593Smuzhiyun /* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */ 105*4882a593Smuzhiyun #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) 106*4882a593Smuzhiyun #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun /* Board Clock */ 109*4882a593Smuzhiyun #if defined(CONFIG_400MHZ_MODE) 110*4882a593Smuzhiyun #define CONFIG_SYS_CLK_FREQ 50000000 111*4882a593Smuzhiyun #else 112*4882a593Smuzhiyun #define CONFIG_SYS_CLK_FREQ 44444444 113*4882a593Smuzhiyun #endif 114*4882a593Smuzhiyun #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ 115*4882a593Smuzhiyun #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 116*4882a593Smuzhiyun #define CONFIG_SYS_TMU_CLK_DIV 4 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun #endif /* __R0P7734_H */ 119