1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2011-2014 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun /* 8*4882a593Smuzhiyun * Corenet DS style board configuration file 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun #ifndef __QEMU_PPCE500_H 11*4882a593Smuzhiyun #define __QEMU_PPCE500_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #undef CONFIG_SYS_TEXT_BASE 14*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0xf01000 /* 15 MB */ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define CONFIG_SYS_MPC85XX_NO_RESETVEC 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define CONFIG_SYS_RAMBOOT 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define CONFIG_PCI1 1 /* PCI controller 1 */ 21*4882a593Smuzhiyun #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 22*4882a593Smuzhiyun #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define CONFIG_ENV_OVERWRITE 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define CONFIG_ENABLE_36BIT_PHYS 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define CONFIG_ADDR_MAP 29*4882a593Smuzhiyun #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 32*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_END 0x00400000 33*4882a593Smuzhiyun #define CONFIG_SYS_ALT_MEMTEST 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* Needed to fill the ccsrbar pointer */ 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* Virtual address to CCSRBAR */ 38*4882a593Smuzhiyun #define CONFIG_SYS_CCSRBAR 0xe0000000 39*4882a593Smuzhiyun /* Physical address should be a function call */ 40*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 41*4882a593Smuzhiyun extern unsigned long long get_phys_ccsrbar_addr_early(void); 42*4882a593Smuzhiyun #define CONFIG_SYS_CCSRBAR_PHYS_HIGH (get_phys_ccsrbar_addr_early() >> 32) 43*4882a593Smuzhiyun #define CONFIG_SYS_CCSRBAR_PHYS_LOW get_phys_ccsrbar_addr_early() 44*4882a593Smuzhiyun #else 45*4882a593Smuzhiyun #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 46*4882a593Smuzhiyun #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 47*4882a593Smuzhiyun #endif 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* Virtual address range for PCI region maps */ 50*4882a593Smuzhiyun #define CONFIG_SYS_PCI_MAP_START 0x80000000 51*4882a593Smuzhiyun #define CONFIG_SYS_PCI_MAP_END 0xe8000000 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* Virtual address to a temporary map if we need it (max 128MB) */ 54*4882a593Smuzhiyun #define CONFIG_SYS_TMPVIRT 0xe8000000 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* 57*4882a593Smuzhiyun * DDR Setup 58*4882a593Smuzhiyun */ 59*4882a593Smuzhiyun #define CONFIG_VERY_BIG_RAM 60*4882a593Smuzhiyun #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 61*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #define CONFIG_CHIP_SELECTS_PER_CTRL 0 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #define CONFIG_SYS_CLK_FREQ 33000000 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #define CONFIG_SYS_BOOT_BLOCK 0x00000000 /* boot TLB */ 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun #define CONFIG_HWCONFIG 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #define CONFIG_SYS_INIT_RAM_ADDR 0x00100000 74*4882a593Smuzhiyun #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0x0 75*4882a593Smuzhiyun #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0x00100000 76*4882a593Smuzhiyun /* The assembler doesn't like typecast */ 77*4882a593Smuzhiyun #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 78*4882a593Smuzhiyun ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 79*4882a593Smuzhiyun CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 80*4882a593Smuzhiyun #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 83*4882a593Smuzhiyun GENERATED_GBL_DATA_SIZE) 84*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 87*4882a593Smuzhiyun #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun #define CONFIG_CONS_INDEX 1 90*4882a593Smuzhiyun #define CONFIG_SYS_NS16550_SERIAL 91*4882a593Smuzhiyun #define CONFIG_SYS_NS16550_REG_SIZE 1 92*4882a593Smuzhiyun #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)) 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun #define CONFIG_SYS_BAUDRATE_TABLE \ 95*4882a593Smuzhiyun {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 98*4882a593Smuzhiyun #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun /* 101*4882a593Smuzhiyun * General PCI 102*4882a593Smuzhiyun * Memory space is mapped 1-1, but I/O space must start from 0. 103*4882a593Smuzhiyun */ 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun #ifdef CONFIG_PCI 106*4882a593Smuzhiyun #define CONFIG_PCI_INDIRECT_BRIDGE 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 109*4882a593Smuzhiyun #endif /* CONFIG_PCI */ 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun #define CONFIG_LBA48 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun /* 114*4882a593Smuzhiyun * Environment 115*4882a593Smuzhiyun */ 116*4882a593Smuzhiyun #define CONFIG_ENV_SIZE 0x2000 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun #define CONFIG_LOADS_ECHO /* echo on for serial download */ 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun #define CONFIG_LAST_STAGE_INIT 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun /* 123*4882a593Smuzhiyun * Command line configuration. 124*4882a593Smuzhiyun */ 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun /* 127*4882a593Smuzhiyun * Miscellaneous configurable options 128*4882a593Smuzhiyun */ 129*4882a593Smuzhiyun #define CONFIG_SYS_LONGHELP /* undef to save memory */ 130*4882a593Smuzhiyun #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 131*4882a593Smuzhiyun #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 132*4882a593Smuzhiyun #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun /* 135*4882a593Smuzhiyun * For booting Linux, the board info and command line data 136*4882a593Smuzhiyun * have to be in the first 64 MB of memory, since this is 137*4882a593Smuzhiyun * the maximum mapped by the Linux kernel during initialization. 138*4882a593Smuzhiyun */ 139*4882a593Smuzhiyun #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 140*4882a593Smuzhiyun #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun /* 143*4882a593Smuzhiyun * Environment Configuration 144*4882a593Smuzhiyun */ 145*4882a593Smuzhiyun #define CONFIG_ROOTPATH "/opt/nfsroot" 146*4882a593Smuzhiyun #define CONFIG_BOOTFILE "uImage" 147*4882a593Smuzhiyun #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun /* default location for tftp and bootm */ 150*4882a593Smuzhiyun #define CONFIG_LOADADDR 1000000 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun #define CONFIG_BOOTCOMMAND \ 153*4882a593Smuzhiyun "test -n \"$qemu_kernel_addr\" && bootm $qemu_kernel_addr - $fdt_addr_r\0" 154*4882a593Smuzhiyun 155*4882a593Smuzhiyun #endif /* __QEMU_PPCE500_H */ 156