1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2010 3*4882a593Smuzhiyun * Ilko Iliev <iliev@ronetix.at> 4*4882a593Smuzhiyun * Asen Dimov <dimov@ronetix.at> 5*4882a593Smuzhiyun * Ronetix GmbH <www.ronetix.at> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * (C) Copyright 2007-2008 8*4882a593Smuzhiyun * Stelian Pop <stelian@popies.net> 9*4882a593Smuzhiyun * Lead Tech Design <www.leadtechdesign.com> 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * Configuation settings for the PM9G45 board. 12*4882a593Smuzhiyun * 13*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 14*4882a593Smuzhiyun */ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #ifndef __CONFIG_H 17*4882a593Smuzhiyun #define __CONFIG_H 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* 20*4882a593Smuzhiyun * SoC must be defined first, before hardware.h is included. 21*4882a593Smuzhiyun * In this case SoC is defined in boards.cfg. 22*4882a593Smuzhiyun */ 23*4882a593Smuzhiyun #include <asm/hardware.h> 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define CONFIG_PM9G45 1 /* It's an Ronetix PM9G45 */ 26*4882a593Smuzhiyun #define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9G45" 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define CONFIG_MACH_TYPE MACH_TYPE_PM9G45 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* ARM asynchronous clock */ 31*4882a593Smuzhiyun #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ 32*4882a593Smuzhiyun #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ 33*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0x73f00000 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define CONFIG_ARCH_CPU_INIT 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 38*4882a593Smuzhiyun #define CONFIG_SETUP_MEMORY_TAGS 1 39*4882a593Smuzhiyun #define CONFIG_INITRD_TAG 1 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #define CONFIG_SKIP_LOWLEVEL_INIT 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* 44*4882a593Smuzhiyun * Hardware drivers 45*4882a593Smuzhiyun */ 46*4882a593Smuzhiyun #define CONFIG_AT91_GPIO 1 47*4882a593Smuzhiyun #define CONFIG_ATMEL_USART 1 48*4882a593Smuzhiyun #define CONFIG_USART_BASE ATMEL_BASE_DBGU 49*4882a593Smuzhiyun #define CONFIG_USART_ID ATMEL_ID_SYS 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define CONFIG_SYS_USE_NANDFLASH 1 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* LED */ 54*4882a593Smuzhiyun #define CONFIG_AT91_LED 55*4882a593Smuzhiyun #define CONFIG_RED_LED GPIO_PIN_PD(31) /* this is the user1 led */ 56*4882a593Smuzhiyun #define CONFIG_GREEN_LED GPIO_PIN_PD(0) /* this is the user2 led */ 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* 60*4882a593Smuzhiyun * BOOTP options 61*4882a593Smuzhiyun */ 62*4882a593Smuzhiyun #define CONFIG_BOOTP_BOOTFILESIZE 1 63*4882a593Smuzhiyun #define CONFIG_BOOTP_BOOTPATH 1 64*4882a593Smuzhiyun #define CONFIG_BOOTP_GATEWAY 1 65*4882a593Smuzhiyun #define CONFIG_BOOTP_HOSTNAME 1 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #define CONFIG_JFFS2_CMDLINE 1 68*4882a593Smuzhiyun #define CONFIG_JFFS2_NAND 1 69*4882a593Smuzhiyun #define CONFIG_JFFS2_DEV "nand0" /* NAND dev jffs2 lives on */ 70*4882a593Smuzhiyun #define CONFIG_JFFS2_PART_OFFSET 0 /* start of jffs2 partition */ 71*4882a593Smuzhiyun #define CONFIG_JFFS2_PART_SIZE (256 * 1024 * 1024) /* partition */ 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun /* SDRAM */ 74*4882a593Smuzhiyun #define CONFIG_NR_DRAM_BANKS 1 75*4882a593Smuzhiyun #define PHYS_SDRAM 0x70000000 76*4882a593Smuzhiyun #define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */ 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun /* NAND flash */ 79*4882a593Smuzhiyun #ifdef CONFIG_CMD_NAND 80*4882a593Smuzhiyun #define CONFIG_SYS_MAX_NAND_DEVICE 1 81*4882a593Smuzhiyun #define CONFIG_SYS_NAND_BASE 0x40000000 82*4882a593Smuzhiyun #define CONFIG_SYS_NAND_DBW_8 1 83*4882a593Smuzhiyun /* our ALE is AD21 */ 84*4882a593Smuzhiyun #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) 85*4882a593Smuzhiyun /* our CLE is AD22 */ 86*4882a593Smuzhiyun #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) 87*4882a593Smuzhiyun #define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14) 88*4882a593Smuzhiyun #define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PD(3) 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun #endif 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun /* Ethernet */ 93*4882a593Smuzhiyun #define CONFIG_MACB 1 94*4882a593Smuzhiyun #define CONFIG_RMII 1 95*4882a593Smuzhiyun #define CONFIG_NET_RETRY_COUNT 20 96*4882a593Smuzhiyun #define CONFIG_RESET_PHY_R 1 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun /* USB */ 99*4882a593Smuzhiyun #define CONFIG_USB_ATMEL 100*4882a593Smuzhiyun #define CONFIG_USB_ATMEL_CLK_SEL_UPLL 101*4882a593Smuzhiyun #define CONFIG_USB_OHCI_NEW 1 102*4882a593Smuzhiyun #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 103*4882a593Smuzhiyun #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00700000 /* _UHP_OHCI_BASE */ 104*4882a593Smuzhiyun #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g45" 105*4882a593Smuzhiyun #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun /* board specific(not enough SRAM) */ 108*4882a593Smuzhiyun #define CONFIG_AT91SAM9G45_LCD_BASE PHYS_SDRAM + 0xE00000 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun #define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM + 0x2000000 /* load addr */ 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM 113*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_END CONFIG_AT91SAM9G45_LCD_BASE 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun /* bootstrap + u-boot + env + linux in nandflash */ 116*4882a593Smuzhiyun #define CONFIG_ENV_OFFSET 0x60000 117*4882a593Smuzhiyun #define CONFIG_ENV_OFFSET_REDUND 0x80000 118*4882a593Smuzhiyun #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ 119*4882a593Smuzhiyun #define CONFIG_BOOTCOMMAND "nand read 0x72000000 0x200000 0x200000; bootm" 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun #define CONFIG_SYS_LONGHELP 1 122*4882a593Smuzhiyun #define CONFIG_CMDLINE_EDITING 1 123*4882a593Smuzhiyun #define CONFIG_AUTO_COMPLETE 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun /* 126*4882a593Smuzhiyun * Size of malloc() pool 127*4882a593Smuzhiyun */ 128*4882a593Smuzhiyun #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024,\ 129*4882a593Smuzhiyun 0x1000) 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM 132*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ 133*4882a593Smuzhiyun GENERATED_GBL_DATA_SIZE) 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun #endif 136