1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) Stefano Babic <sbabic@denx.de> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __PCM058_CONFIG_H 9*4882a593Smuzhiyun #define __PCM058_CONFIG_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <config_distro_defaults.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #ifdef CONFIG_SPL 14*4882a593Smuzhiyun #define CONFIG_SPL_SPI_LOAD 15*4882a593Smuzhiyun #define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024) 16*4882a593Smuzhiyun #include "imx6_spl.h" 17*4882a593Smuzhiyun #endif 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #include "mx6_common.h" 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* Thermal */ 22*4882a593Smuzhiyun #define CONFIG_IMX_THERMAL 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* Serial */ 25*4882a593Smuzhiyun #define CONFIG_MXC_UART 26*4882a593Smuzhiyun #define CONFIG_MXC_UART_BASE UART2_BASE 27*4882a593Smuzhiyun #define CONSOLE_DEV "ttymxc1" 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* Early setup */ 32*4882a593Smuzhiyun #define CONFIG_DISPLAY_BOARDINFO_LATE 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* Size of malloc() pool */ 36*4882a593Smuzhiyun #define CONFIG_SYS_MALLOC_LEN (8 * SZ_1M) 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* Ethernet */ 39*4882a593Smuzhiyun #define CONFIG_FEC_MXC 40*4882a593Smuzhiyun #define CONFIG_MII 41*4882a593Smuzhiyun #define IMX_FEC_BASE ENET_BASE_ADDR 42*4882a593Smuzhiyun #define CONFIG_FEC_XCV_TYPE RGMII 43*4882a593Smuzhiyun #define CONFIG_ETHPRIME "FEC" 44*4882a593Smuzhiyun #define CONFIG_FEC_MXC_PHYADDR 3 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* SPI Flash */ 47*4882a593Smuzhiyun #define CONFIG_MXC_SPI 48*4882a593Smuzhiyun #define CONFIG_SF_DEFAULT_BUS 0 49*4882a593Smuzhiyun #define CONFIG_SF_DEFAULT_CS 0 50*4882a593Smuzhiyun #define CONFIG_SF_DEFAULT_SPEED 20000000 51*4882a593Smuzhiyun #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* I2C Configs */ 54*4882a593Smuzhiyun #define CONFIG_SYS_I2C 55*4882a593Smuzhiyun #define CONFIG_SYS_I2C_MXC 56*4882a593Smuzhiyun #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 2 */ 57*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SPEED 100000 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #ifndef CONFIG_SPL_BUILD 60*4882a593Smuzhiyun /* Enable NAND support */ 61*4882a593Smuzhiyun #define CONFIG_SYS_MAX_NAND_DEVICE 1 62*4882a593Smuzhiyun #define CONFIG_SYS_NAND_BASE 0x40000000 63*4882a593Smuzhiyun #define CONFIG_SYS_NAND_5_ADDR_CYCLE 64*4882a593Smuzhiyun #define CONFIG_SYS_NAND_ONFI_DETECTION 65*4882a593Smuzhiyun #endif 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun /* DMA stuff, needed for GPMI/MXS NAND support */ 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun /* Filesystem support */ 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* Physical Memory Map */ 72*4882a593Smuzhiyun #define CONFIG_NR_DRAM_BANKS 1 73*4882a593Smuzhiyun #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM 76*4882a593Smuzhiyun #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 77*4882a593Smuzhiyun #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_OFFSET \ 80*4882a593Smuzhiyun (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 81*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_ADDR \ 82*4882a593Smuzhiyun (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun /* MMC Configs */ 85*4882a593Smuzhiyun #define CONFIG_SYS_FSL_ESDHC_ADDR 0 86*4882a593Smuzhiyun #define CONFIG_SYS_FSL_USDHC_NUM 1 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun /* Environment organization */ 89*4882a593Smuzhiyun #define CONFIG_ENV_SIZE (16 * 1024) 90*4882a593Smuzhiyun #define CONFIG_ENV_OFFSET (1024 * SZ_1K) 91*4882a593Smuzhiyun #define CONFIG_ENV_SECT_SIZE (64 * SZ_1K) 92*4882a593Smuzhiyun #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS 93*4882a593Smuzhiyun #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS 94*4882a593Smuzhiyun #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE 95*4882a593Smuzhiyun #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 96*4882a593Smuzhiyun #define CONFIG_SYS_REDUNDAND_ENVIRONMENT 97*4882a593Smuzhiyun #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ 98*4882a593Smuzhiyun CONFIG_ENV_SECT_SIZE) 99*4882a593Smuzhiyun #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun #ifdef CONFIG_ENV_IS_IN_NAND 102*4882a593Smuzhiyun #define CONFIG_ENV_OFFSET (0x1E0000) 103*4882a593Smuzhiyun #define CONFIG_ENV_SECT_SIZE (128 * SZ_1K) 104*4882a593Smuzhiyun #endif 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun #endif 107