1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (c) 2013-2016, NVIDIA CORPORATION. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _P2771_0000_H 8*4882a593Smuzhiyun #define _P2771_0000_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <linux/sizes.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include "tegra186-common.h" 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* High-level configuration options */ 15*4882a593Smuzhiyun #define CONFIG_TEGRA_BOARD_STRING "NVIDIA P2771-0000" 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* I2C */ 18*4882a593Smuzhiyun #define CONFIG_SYS_I2C_TEGRA 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* Environment in eMMC, at the end of 2nd "boot sector" */ 21*4882a593Smuzhiyun #define CONFIG_SYS_MMC_ENV_DEV 0 22*4882a593Smuzhiyun #define CONFIG_SYS_MMC_ENV_PART 2 23*4882a593Smuzhiyun #define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* PCI host support */ 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #include "tegra-common-post.h" 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* Crystal is 38.4MHz. clk_m runs at half that rate */ 30*4882a593Smuzhiyun #define COUNTER_FREQUENCY 19200000 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #endif 33