1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * Copyright (C) 2014 Bachmann electronic GmbH 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __CONFIG_H 9*4882a593Smuzhiyun #define __CONFIG_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include "mx6_common.h" 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* Size of malloc() pool */ 14*4882a593Smuzhiyun #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define CONFIG_MISC_INIT_R 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* UART Configs */ 19*4882a593Smuzhiyun #define CONFIG_MXC_UART 20*4882a593Smuzhiyun #define CONFIG_MXC_UART_BASE UART1_BASE 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* SF Configs */ 23*4882a593Smuzhiyun #define CONFIG_SPI 24*4882a593Smuzhiyun #define CONFIG_MXC_SPI 25*4882a593Smuzhiyun #define CONFIG_SF_DEFAULT_BUS 2 26*4882a593Smuzhiyun #define CONFIG_SF_DEFAULT_CS 0 27*4882a593Smuzhiyun #define CONFIG_SF_DEFAULT_SPEED 25000000 28*4882a593Smuzhiyun #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* IO expander */ 31*4882a593Smuzhiyun #define CONFIG_PCA953X 32*4882a593Smuzhiyun #define CONFIG_SYS_I2C_PCA953X_ADDR 0x20 33*4882a593Smuzhiyun #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x20, 16} } 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* I2C Configs */ 36*4882a593Smuzhiyun #define CONFIG_SYS_I2C 37*4882a593Smuzhiyun #define CONFIG_SYS_I2C_MXC 38*4882a593Smuzhiyun #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 39*4882a593Smuzhiyun #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 40*4882a593Smuzhiyun #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 41*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SPEED 100000 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* OCOTP Configs */ 44*4882a593Smuzhiyun #define CONFIG_IMX_OTP 45*4882a593Smuzhiyun #define IMX_OTP_BASE OCOTP_BASE_ADDR 46*4882a593Smuzhiyun #define IMX_OTP_ADDR_MAX 0x7F 47*4882a593Smuzhiyun #define IMX_OTP_DATA_ERROR_VAL 0xBADABADA 48*4882a593Smuzhiyun #define IMX_OTPWRITE_ENABLED 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* MMC Configs */ 51*4882a593Smuzhiyun #define CONFIG_SYS_FSL_ESDHC_ADDR 0 52*4882a593Smuzhiyun #define CONFIG_SYS_FSL_USDHC_NUM 2 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* USB Configs */ 55*4882a593Smuzhiyun #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) 56*4882a593Smuzhiyun #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* 59*4882a593Smuzhiyun * SATA Configs 60*4882a593Smuzhiyun */ 61*4882a593Smuzhiyun #ifdef CONFIG_CMD_SATA 62*4882a593Smuzhiyun #define CONFIG_DWC_AHSATA 63*4882a593Smuzhiyun #define CONFIG_SYS_SATA_MAX_DEVICE 1 64*4882a593Smuzhiyun #define CONFIG_DWC_AHSATA_PORT_ID 0 65*4882a593Smuzhiyun #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR 66*4882a593Smuzhiyun #define CONFIG_LBA48 67*4882a593Smuzhiyun #define CONFIG_LIBATA 68*4882a593Smuzhiyun #endif 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun /* SPL */ 71*4882a593Smuzhiyun #ifdef CONFIG_SPL 72*4882a593Smuzhiyun #include "imx6_spl.h" 73*4882a593Smuzhiyun #define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024) 74*4882a593Smuzhiyun #define CONFIG_SPL_SPI_LOAD 75*4882a593Smuzhiyun #endif 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun #define CONFIG_FEC_MXC 78*4882a593Smuzhiyun #define CONFIG_MII 79*4882a593Smuzhiyun #define IMX_FEC_BASE ENET_BASE_ADDR 80*4882a593Smuzhiyun #define CONFIG_FEC_XCV_TYPE MII100 81*4882a593Smuzhiyun #define CONFIG_ETHPRIME "FEC" 82*4882a593Smuzhiyun #define CONFIG_FEC_MXC_PHYADDR 0x5 83*4882a593Smuzhiyun #define CONFIG_PHY_SMSC 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun #ifndef CONFIG_SPL 86*4882a593Smuzhiyun #define CONFIG_ENV_EEPROM_IS_ON_I2C 87*4882a593Smuzhiyun #define CONFIG_SYS_I2C_EEPROM_BUS 1 88*4882a593Smuzhiyun #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 89*4882a593Smuzhiyun #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 90*4882a593Smuzhiyun #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 91*4882a593Smuzhiyun #endif 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun #define CONFIG_PREBOOT "" 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun /* Thermal support */ 96*4882a593Smuzhiyun #define CONFIG_IMX_THERMAL 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun /* Physical Memory Map */ 99*4882a593Smuzhiyun #define CONFIG_NR_DRAM_BANKS 1 100*4882a593Smuzhiyun #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM 103*4882a593Smuzhiyun #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 104*4882a593Smuzhiyun #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_OFFSET \ 107*4882a593Smuzhiyun (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 108*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_ADDR \ 109*4882a593Smuzhiyun (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun /* Environment organization */ 112*4882a593Smuzhiyun #define CONFIG_ENV_SIZE (64 * 1024) /* 64 kb */ 113*4882a593Smuzhiyun #define CONFIG_ENV_OFFSET (1024 * 1024) 114*4882a593Smuzhiyun /* M25P16 has an erase size of 64 KiB */ 115*4882a593Smuzhiyun #define CONFIG_ENV_SECT_SIZE (64 * 1024) 116*4882a593Smuzhiyun #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS 117*4882a593Smuzhiyun #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS 118*4882a593Smuzhiyun #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE 119*4882a593Smuzhiyun #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun #define CONFIG_BOOTP_SERVERIP 122*4882a593Smuzhiyun #define CONFIG_BOOTP_BOOTFILE 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun #endif /* __CONFIG_H */ 125