1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2011 Samsung Electronics 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Configuration settings for the SAMSUNG ORIGEN (EXYNOS4210) board. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __CONFIG_ORIGEN_H 10*4882a593Smuzhiyun #define __CONFIG_ORIGEN_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <configs/exynos4-common.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* High Level Configuration Options */ 15*4882a593Smuzhiyun #define CONFIG_EXYNOS4210 1 /* which is a EXYNOS4210 SoC */ 16*4882a593Smuzhiyun #define CONFIG_ORIGEN 1 /* working with ORIGEN*/ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define CONFIG_SYS_DCACHE_OFF 1 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* ORIGEN has 4 bank of DRAM */ 21*4882a593Smuzhiyun #define CONFIG_NR_DRAM_BANKS 4 22*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_BASE 0x40000000 23*4882a593Smuzhiyun #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE 24*4882a593Smuzhiyun #define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* memtest works on */ 27*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 28*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x6000000) 29*4882a593Smuzhiyun #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0x43E00000 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define CONFIG_MACH_TYPE MACH_TYPE_ORIGEN 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* select serial console configuration */ 36*4882a593Smuzhiyun #define CONFIG_SERIAL2 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* Console configuration */ 39*4882a593Smuzhiyun #define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */ 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define CONFIG_SYS_MONITOR_BASE 0x00000000 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* Power Down Modes */ 46*4882a593Smuzhiyun #define S5P_CHECK_SLEEP 0x00000BAD 47*4882a593Smuzhiyun #define S5P_CHECK_DIDLE 0xBAD00000 48*4882a593Smuzhiyun #define S5P_CHECK_LPA 0xABAD0000 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #define CONFIG_SUPPORT_RAW_INITRD 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* MMC SPL */ 53*4882a593Smuzhiyun #define COPY_BL2_FNPTR_ADDR 0x02020030 54*4882a593Smuzhiyun #define CONFIG_SPL_TEXT_BASE 0x02021410 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #define CONFIG_EXTRA_ENV_SETTINGS \ 57*4882a593Smuzhiyun "loadaddr=0x40007000\0" \ 58*4882a593Smuzhiyun "rdaddr=0x48000000\0" \ 59*4882a593Smuzhiyun "kerneladdr=0x40007000\0" \ 60*4882a593Smuzhiyun "ramdiskaddr=0x48000000\0" \ 61*4882a593Smuzhiyun "console=ttySAC2,115200n8\0" \ 62*4882a593Smuzhiyun "mmcdev=0\0" \ 63*4882a593Smuzhiyun "bootenv=uEnv.txt\0" \ 64*4882a593Smuzhiyun "loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ 65*4882a593Smuzhiyun "importbootenv=echo Importing environment from mmc ...; " \ 66*4882a593Smuzhiyun "env import -t $loadaddr $filesize\0" \ 67*4882a593Smuzhiyun "loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 68*4882a593Smuzhiyun "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \ 69*4882a593Smuzhiyun "source ${loadaddr}\0" 70*4882a593Smuzhiyun #define CONFIG_BOOTCOMMAND \ 71*4882a593Smuzhiyun "if mmc rescan; then " \ 72*4882a593Smuzhiyun "echo SD/MMC found on device ${mmcdev};" \ 73*4882a593Smuzhiyun "if run loadbootenv; then " \ 74*4882a593Smuzhiyun "echo Loaded environment from ${bootenv};" \ 75*4882a593Smuzhiyun "run importbootenv;" \ 76*4882a593Smuzhiyun "fi;" \ 77*4882a593Smuzhiyun "if test -n $uenvcmd; then " \ 78*4882a593Smuzhiyun "echo Running uenvcmd ...;" \ 79*4882a593Smuzhiyun "run uenvcmd;" \ 80*4882a593Smuzhiyun "fi;" \ 81*4882a593Smuzhiyun "if run loadbootscript; then " \ 82*4882a593Smuzhiyun "run bootscript; " \ 83*4882a593Smuzhiyun "fi; " \ 84*4882a593Smuzhiyun "fi;" \ 85*4882a593Smuzhiyun "load mmc ${mmcdev} ${loadaddr} uImage; bootm ${loadaddr} " 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun #define CONFIG_CLK_1000_400_200 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun /* MIU (Memory Interleaving Unit) */ 90*4882a593Smuzhiyun #define CONFIG_MIU_2BIT_21_7_INTERLEAVED 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun #define CONFIG_SYS_MMC_ENV_DEV 0 93*4882a593Smuzhiyun #define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */ 94*4882a593Smuzhiyun #define RESERVE_BLOCK_SIZE (512) 95*4882a593Smuzhiyun #define BL1_SIZE (16 << 10) /*16 K reserved for BL1*/ 96*4882a593Smuzhiyun #define CONFIG_ENV_OFFSET (RESERVE_BLOCK_SIZE + BL1_SIZE) 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun #define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024) 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_ADDR 0x02040000 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun /* U-Boot copy size from boot Media to DRAM.*/ 103*4882a593Smuzhiyun #define COPY_BL2_SIZE 0x80000 104*4882a593Smuzhiyun #define BL2_START_OFFSET ((CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)/512) 105*4882a593Smuzhiyun #define BL2_SIZE_BLOC_COUNT (COPY_BL2_SIZE/512) 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun #endif /* __CONFIG_H */ 108