1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2015 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Configuration settings for the Freescale i.MX7. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __MX7_COMMON_H 10*4882a593Smuzhiyun #define __MX7_COMMON_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <linux/sizes.h> 13*4882a593Smuzhiyun #include <asm/arch/imx-regs.h> 14*4882a593Smuzhiyun #include <asm/mach-imx/gpio.h> 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #ifndef CONFIG_MX7 17*4882a593Smuzhiyun #define CONFIG_MX7 18*4882a593Smuzhiyun #endif 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* Timer settings */ 21*4882a593Smuzhiyun #define CONFIG_MXC_GPT_HCLK 22*4882a593Smuzhiyun #define CONFIG_SYSCOUNTER_TIMER 23*4882a593Smuzhiyun #define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */ 24*4882a593Smuzhiyun #define COUNTER_FREQUENCY CONFIG_SC_TIMER_CLK 25*4882a593Smuzhiyun #define CONFIG_SYS_FSL_CLK 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define CONFIG_SYS_BOOTM_LEN 0x1000000 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* Enable iomux-lpsr support */ 30*4882a593Smuzhiyun #define CONFIG_IOMUX_LPSR 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define CONFIG_LOADADDR 0x80800000 33*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0x87800000 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* allow to overwrite serial and ethaddr */ 36*4882a593Smuzhiyun #define CONFIG_ENV_OVERWRITE 37*4882a593Smuzhiyun #define CONFIG_CONS_INDEX 1 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* Miscellaneous configurable options */ 40*4882a593Smuzhiyun #define CONFIG_SYS_LONGHELP 41*4882a593Smuzhiyun #define CONFIG_CMDLINE_EDITING 42*4882a593Smuzhiyun #define CONFIG_AUTO_COMPLETE 43*4882a593Smuzhiyun #define CONFIG_SYS_CBSIZE 512 44*4882a593Smuzhiyun #define CONFIG_SYS_MAXARGS 32 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #ifndef CONFIG_SYS_DCACHE_OFF 47*4882a593Smuzhiyun #endif 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* GPIO */ 50*4882a593Smuzhiyun #define CONFIG_MXC_GPIO 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* UART */ 53*4882a593Smuzhiyun #define CONFIG_MXC_UART 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* MMC */ 56*4882a593Smuzhiyun #define CONFIG_BOUNCE_BUFFER 57*4882a593Smuzhiyun #define CONFIG_FSL_ESDHC 58*4882a593Smuzhiyun #define CONFIG_FSL_USDHC 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /* Fuses */ 61*4882a593Smuzhiyun #define CONFIG_MXC_OCOTP 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #define CONFIG_ARMV7_SECURE_BASE 0x00900000 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun /* Secure boot (HAB) support */ 66*4882a593Smuzhiyun #ifdef CONFIG_SECURE_BOOT 67*4882a593Smuzhiyun #define CONFIG_CSF_SIZE 0x2000 68*4882a593Smuzhiyun #endif 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun #endif 71