1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2012 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Configuration settings for the Freescale i.MX6Q SabreSD board. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __MX6SABRESD_CONFIG_H 10*4882a593Smuzhiyun #define __MX6SABRESD_CONFIG_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifdef CONFIG_SPL 13*4882a593Smuzhiyun #include "imx6_spl.h" 14*4882a593Smuzhiyun #endif 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define CONFIG_MACH_TYPE 3980 17*4882a593Smuzhiyun #define CONFIG_MXC_UART_BASE UART1_BASE 18*4882a593Smuzhiyun #define CONSOLE_DEV "ttymxc0" 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #include "mx6sabre_common.h" 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* Falcon Mode */ 25*4882a593Smuzhiyun #define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" 26*4882a593Smuzhiyun #define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" 27*4882a593Smuzhiyun #define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* Falcon Mode - MMC support: args@1MB kernel@2MB */ 30*4882a593Smuzhiyun #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */ 31*4882a593Smuzhiyun #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512) 32*4882a593Smuzhiyun #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 /* 2MB */ 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define CONFIG_SYS_FSL_USDHC_NUM 3 35*4882a593Smuzhiyun #if defined(CONFIG_ENV_IS_IN_MMC) 36*4882a593Smuzhiyun #define CONFIG_SYS_MMC_ENV_DEV 1 /* SDHC3 */ 37*4882a593Smuzhiyun #endif 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #ifdef CONFIG_CMD_PCI 40*4882a593Smuzhiyun #define CONFIG_PCI_SCAN_SHOW 41*4882a593Smuzhiyun #define CONFIG_PCIE_IMX 42*4882a593Smuzhiyun #define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12) 43*4882a593Smuzhiyun #define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(3, 19) 44*4882a593Smuzhiyun #endif 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* I2C Configs */ 47*4882a593Smuzhiyun #define CONFIG_SYS_I2C 48*4882a593Smuzhiyun #define CONFIG_SYS_I2C_MXC 49*4882a593Smuzhiyun #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 50*4882a593Smuzhiyun #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 51*4882a593Smuzhiyun #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 52*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SPEED 100000 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* PMIC */ 55*4882a593Smuzhiyun #define CONFIG_POWER 56*4882a593Smuzhiyun #define CONFIG_POWER_I2C 57*4882a593Smuzhiyun #define CONFIG_POWER_PFUZE100 58*4882a593Smuzhiyun #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /* USB Configs */ 61*4882a593Smuzhiyun #ifdef CONFIG_CMD_USB 62*4882a593Smuzhiyun #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 63*4882a593Smuzhiyun #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) 64*4882a593Smuzhiyun #define CONFIG_MXC_USB_FLAGS 0 65*4882a593Smuzhiyun #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Enabled USB controller number */ 66*4882a593Smuzhiyun #endif 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun #endif /* __MX6SABRESD_CONFIG_H */ 69