1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2010, Stefano Babic <sbabic@denx.de> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Configuration for the MX35pdk Freescale board. 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #ifndef __CONFIG_H 14*4882a593Smuzhiyun #define __CONFIG_H 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #include <asm/arch/imx-regs.h> 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* High Level Configuration Options */ 19*4882a593Smuzhiyun #define CONFIG_MX35 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define CONFIG_SYS_FSL_CLK 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun /* Set TEXT at the beginning of the NOR flash */ 24*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0xA0000000 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 27*4882a593Smuzhiyun #define CONFIG_REVISION_TAG 28*4882a593Smuzhiyun #define CONFIG_SETUP_MEMORY_TAGS 29*4882a593Smuzhiyun #define CONFIG_INITRD_TAG 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* 32*4882a593Smuzhiyun * Size of malloc() pool 33*4882a593Smuzhiyun */ 34*4882a593Smuzhiyun #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* 37*4882a593Smuzhiyun * Hardware drivers 38*4882a593Smuzhiyun */ 39*4882a593Smuzhiyun #define CONFIG_SYS_I2C 40*4882a593Smuzhiyun #define CONFIG_SYS_I2C_MXC 41*4882a593Smuzhiyun #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 42*4882a593Smuzhiyun #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 43*4882a593Smuzhiyun #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 44*4882a593Smuzhiyun #define CONFIG_MXC_SPI 45*4882a593Smuzhiyun #define CONFIG_MXC_GPIO 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* 48*4882a593Smuzhiyun * PMIC Configs 49*4882a593Smuzhiyun */ 50*4882a593Smuzhiyun #define CONFIG_POWER 51*4882a593Smuzhiyun #define CONFIG_POWER_I2C 52*4882a593Smuzhiyun #define CONFIG_POWER_FSL 53*4882a593Smuzhiyun #define CONFIG_POWER_FSL_MC13892 54*4882a593Smuzhiyun #define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x08 55*4882a593Smuzhiyun #define CONFIG_RTC_MC13XXX 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /* 58*4882a593Smuzhiyun * MFD MC9SDZ60 59*4882a593Smuzhiyun */ 60*4882a593Smuzhiyun #define CONFIG_FSL_MC9SDZ60 61*4882a593Smuzhiyun #define CONFIG_SYS_FSL_MC9SDZ60_I2C_ADDR 0x69 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun /* 64*4882a593Smuzhiyun * UART (console) 65*4882a593Smuzhiyun */ 66*4882a593Smuzhiyun #define CONFIG_MXC_UART 67*4882a593Smuzhiyun #define CONFIG_MXC_UART_BASE UART1_BASE 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun /* allow to overwrite serial and ethaddr */ 70*4882a593Smuzhiyun #define CONFIG_ENV_OVERWRITE 71*4882a593Smuzhiyun #define CONFIG_CONS_INDEX 1 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun /* 74*4882a593Smuzhiyun * Command definition 75*4882a593Smuzhiyun */ 76*4882a593Smuzhiyun #define CONFIG_BOOTP_SUBNETMASK 77*4882a593Smuzhiyun #define CONFIG_BOOTP_GATEWAY 78*4882a593Smuzhiyun #define CONFIG_BOOTP_DNS 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun #define CONFIG_NET_RETRY_COUNT 100 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun #define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */ 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun /* 86*4882a593Smuzhiyun * Ethernet on the debug board (SMC911) 87*4882a593Smuzhiyun */ 88*4882a593Smuzhiyun #define CONFIG_SMC911X 89*4882a593Smuzhiyun #define CONFIG_SMC911X_16_BIT 1 90*4882a593Smuzhiyun #define CONFIG_SMC911X_BASE CS5_BASE_ADDR 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun #define CONFIG_HAS_ETH1 93*4882a593Smuzhiyun #define CONFIG_ETHPRIME 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun /* 96*4882a593Smuzhiyun * Ethernet on SOC (FEC) 97*4882a593Smuzhiyun */ 98*4882a593Smuzhiyun #define CONFIG_FEC_MXC 99*4882a593Smuzhiyun #define IMX_FEC_BASE FEC_BASE_ADDR 100*4882a593Smuzhiyun #define CONFIG_FEC_MXC_PHYADDR 0x1F 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun #define CONFIG_MII 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun #define CONFIG_ARP_TIMEOUT 200UL 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun /* 107*4882a593Smuzhiyun * Miscellaneous configurable options 108*4882a593Smuzhiyun */ 109*4882a593Smuzhiyun #define CONFIG_SYS_LONGHELP /* undef to save memory */ 110*4882a593Smuzhiyun #define CONFIG_CMDLINE_EDITING 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun #define CONFIG_AUTO_COMPLETE 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ 115*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_END 0x10000 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun /* 120*4882a593Smuzhiyun * Physical Memory Map 121*4882a593Smuzhiyun */ 122*4882a593Smuzhiyun #define CONFIG_NR_DRAM_BANKS 2 123*4882a593Smuzhiyun #define PHYS_SDRAM_1 CSD0_BASE_ADDR 124*4882a593Smuzhiyun #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) 125*4882a593Smuzhiyun #define PHYS_SDRAM_2 CSD1_BASE_ADDR 126*4882a593Smuzhiyun #define PHYS_SDRAM_2_SIZE (128 * 1024 * 1024) 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_BASE CSD0_BASE_ADDR 129*4882a593Smuzhiyun #define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR + 0x10000) 130*4882a593Smuzhiyun #define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE / 2) 131*4882a593Smuzhiyun #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 132*4882a593Smuzhiyun GENERATED_GBL_DATA_SIZE) 133*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 134*4882a593Smuzhiyun CONFIG_SYS_GBL_DATA_OFFSET) 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun /* 137*4882a593Smuzhiyun * MTD Command for mtdparts 138*4882a593Smuzhiyun */ 139*4882a593Smuzhiyun #define CONFIG_FLASH_CFI_MTD 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun /* 142*4882a593Smuzhiyun * FLASH and environment organization 143*4882a593Smuzhiyun */ 144*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_BASE CS0_BASE_ADDR 145*4882a593Smuzhiyun #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 146*4882a593Smuzhiyun #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ 147*4882a593Smuzhiyun /* Monitor at beginning of flash */ 148*4882a593Smuzhiyun #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 149*4882a593Smuzhiyun #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun #define CONFIG_ENV_SECT_SIZE (128 * 1024) 152*4882a593Smuzhiyun #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun /* Address and size of Redundant Environment Sector */ 155*4882a593Smuzhiyun #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) 156*4882a593Smuzhiyun #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ 159*4882a593Smuzhiyun CONFIG_SYS_MONITOR_LEN) 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun #if defined(CONFIG_FSL_ENV_IN_NAND) 162*4882a593Smuzhiyun #define CONFIG_ENV_OFFSET (1024 * 1024) 163*4882a593Smuzhiyun #endif 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun /* 166*4882a593Smuzhiyun * CFI FLASH driver setup 167*4882a593Smuzhiyun */ 168*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */ 169*4882a593Smuzhiyun #define CONFIG_FLASH_CFI_DRIVER 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun /* A non-standard buffered write algorithm */ 172*4882a593Smuzhiyun #define CONFIG_FLASH_SPANSION_S29WS_N 173*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* faster */ 174*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_PROTECTION /* Use hardware sector protection */ 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun /* 177*4882a593Smuzhiyun * NAND FLASH driver setup 178*4882a593Smuzhiyun */ 179*4882a593Smuzhiyun #define CONFIG_MXC_NAND_REGS_BASE (NFC_BASE_ADDR) 180*4882a593Smuzhiyun #define CONFIG_SYS_MAX_NAND_DEVICE 1 181*4882a593Smuzhiyun #define CONFIG_SYS_NAND_BASE (NFC_BASE_ADDR) 182*4882a593Smuzhiyun #define CONFIG_MXC_NAND_HWECC 183*4882a593Smuzhiyun #define CONFIG_SYS_NAND_LARGEPAGE 184*4882a593Smuzhiyun 185*4882a593Smuzhiyun /* EHCI driver */ 186*4882a593Smuzhiyun #define CONFIG_EHCI_IS_TDI 187*4882a593Smuzhiyun #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 188*4882a593Smuzhiyun #define CONFIG_USB_EHCI_MXC 189*4882a593Smuzhiyun #define CONFIG_MXC_USB_PORT 0 190*4882a593Smuzhiyun #define CONFIG_MXC_USB_FLAGS (MXC_EHCI_INTERFACE_DIFF_UNI | \ 191*4882a593Smuzhiyun MXC_EHCI_POWER_PINS_ENABLED | \ 192*4882a593Smuzhiyun MXC_EHCI_OC_PIN_ACTIVE_LOW) 193*4882a593Smuzhiyun #define CONFIG_MXC_USB_PORTSC (MXC_EHCI_UTMI_16BIT | MXC_EHCI_MODE_UTMI) 194*4882a593Smuzhiyun 195*4882a593Smuzhiyun /* mmc driver */ 196*4882a593Smuzhiyun #define CONFIG_FSL_ESDHC 197*4882a593Smuzhiyun #define CONFIG_SYS_FSL_ESDHC_ADDR 0 198*4882a593Smuzhiyun #define CONFIG_SYS_FSL_ESDHC_NUM 1 199*4882a593Smuzhiyun 200*4882a593Smuzhiyun /* 201*4882a593Smuzhiyun * Default environment and default scripts 202*4882a593Smuzhiyun * to update uboot and load kernel 203*4882a593Smuzhiyun */ 204*4882a593Smuzhiyun 205*4882a593Smuzhiyun #define CONFIG_HOSTNAME "mx35pdk" 206*4882a593Smuzhiyun #define CONFIG_EXTRA_ENV_SETTINGS \ 207*4882a593Smuzhiyun "netdev=eth1\0" \ 208*4882a593Smuzhiyun "ethprime=smc911x\0" \ 209*4882a593Smuzhiyun "nfsargs=setenv bootargs root=/dev/nfs rw " \ 210*4882a593Smuzhiyun "nfsroot=${serverip}:${rootpath}\0" \ 211*4882a593Smuzhiyun "ramargs=setenv bootargs root=/dev/ram rw\0" \ 212*4882a593Smuzhiyun "addip_sta=setenv bootargs ${bootargs} " \ 213*4882a593Smuzhiyun "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 214*4882a593Smuzhiyun ":${hostname}:${netdev}:off panic=1\0" \ 215*4882a593Smuzhiyun "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \ 216*4882a593Smuzhiyun "addip=if test -n ${ipdyn};then run addip_dyn;" \ 217*4882a593Smuzhiyun "else run addip_sta;fi\0" \ 218*4882a593Smuzhiyun "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 219*4882a593Smuzhiyun "addtty=setenv bootargs ${bootargs}" \ 220*4882a593Smuzhiyun " console=ttymxc0,${baudrate}\0" \ 221*4882a593Smuzhiyun "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ 222*4882a593Smuzhiyun "loadaddr=80800000\0" \ 223*4882a593Smuzhiyun "kernel_addr_r=80800000\0" \ 224*4882a593Smuzhiyun "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \ 225*4882a593Smuzhiyun "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \ 226*4882a593Smuzhiyun "ramdisk_file=" __stringify(CONFIG_HOSTNAME) "/uRamdisk\0" \ 227*4882a593Smuzhiyun "flash_self=run ramargs addip addtty addmtd addmisc;" \ 228*4882a593Smuzhiyun "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 229*4882a593Smuzhiyun "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ 230*4882a593Smuzhiyun "bootm ${kernel_addr}\0" \ 231*4882a593Smuzhiyun "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ 232*4882a593Smuzhiyun "run nfsargs addip addtty addmtd addmisc;" \ 233*4882a593Smuzhiyun "bootm ${kernel_addr_r}\0" \ 234*4882a593Smuzhiyun "net_self_load=tftp ${kernel_addr_r} ${bootfile};" \ 235*4882a593Smuzhiyun "tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \ 236*4882a593Smuzhiyun "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.bin\0" \ 237*4882a593Smuzhiyun "load=tftp ${loadaddr} ${u-boot}\0" \ 238*4882a593Smuzhiyun "uboot_addr=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \ 239*4882a593Smuzhiyun "update=protect off ${uboot_addr} +80000;" \ 240*4882a593Smuzhiyun "erase ${uboot_addr} +80000;" \ 241*4882a593Smuzhiyun "cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \ 242*4882a593Smuzhiyun "upd=if run load;then echo Updating u-boot;if run update;" \ 243*4882a593Smuzhiyun "then echo U-Boot updated;" \ 244*4882a593Smuzhiyun "else echo Error updating u-boot !;" \ 245*4882a593Smuzhiyun "echo Board without bootloader !!;" \ 246*4882a593Smuzhiyun "fi;" \ 247*4882a593Smuzhiyun "else echo U-Boot not downloaded..exiting;fi\0" \ 248*4882a593Smuzhiyun "bootcmd=run net_nfs\0" 249*4882a593Smuzhiyun 250*4882a593Smuzhiyun #endif /* __CONFIG_H */ 251