1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Configuration settings for the MX31ADS Freescale board. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __CONFIG_H 10*4882a593Smuzhiyun #define __CONFIG_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <asm/arch/imx-regs.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* High Level Configuration Options */ 15*4882a593Smuzhiyun #define CONFIG_MX31 1 /* This is a mx31 */ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0xA0000000 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define CONFIG_MACH_TYPE MACH_TYPE_MX31ADS 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 22*4882a593Smuzhiyun #define CONFIG_SETUP_MEMORY_TAGS 1 23*4882a593Smuzhiyun #define CONFIG_INITRD_TAG 1 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* 26*4882a593Smuzhiyun * Size of malloc() pool 27*4882a593Smuzhiyun */ 28*4882a593Smuzhiyun #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* 31*4882a593Smuzhiyun * Hardware drivers 32*4882a593Smuzhiyun */ 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define CONFIG_MXC_UART 35*4882a593Smuzhiyun #define CONFIG_MXC_UART_BASE UART1_BASE 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define CONFIG_HARD_SPI 1 38*4882a593Smuzhiyun #define CONFIG_MXC_SPI 1 39*4882a593Smuzhiyun #define CONFIG_DEFAULT_SPI_BUS 1 40*4882a593Smuzhiyun #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) 41*4882a593Smuzhiyun #define CONFIG_MXC_GPIO 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* PMIC Controller */ 44*4882a593Smuzhiyun #define CONFIG_POWER 45*4882a593Smuzhiyun #define CONFIG_POWER_SPI 46*4882a593Smuzhiyun #define CONFIG_POWER_FSL 47*4882a593Smuzhiyun #define CONFIG_FSL_PMIC_BUS 1 48*4882a593Smuzhiyun #define CONFIG_FSL_PMIC_CS 0 49*4882a593Smuzhiyun #define CONFIG_FSL_PMIC_CLK 1000000 50*4882a593Smuzhiyun #define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) 51*4882a593Smuzhiyun #define CONFIG_FSL_PMIC_BITLEN 32 52*4882a593Smuzhiyun #define CONFIG_RTC_MC13XXX 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* allow to overwrite serial and ethaddr */ 55*4882a593Smuzhiyun #define CONFIG_ENV_OVERWRITE 56*4882a593Smuzhiyun #define CONFIG_CONS_INDEX 1 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */ 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #define CONFIG_EXTRA_ENV_SETTINGS \ 61*4882a593Smuzhiyun "netdev=eth0\0" \ 62*4882a593Smuzhiyun "uboot_addr=0xa0000000\0" \ 63*4882a593Smuzhiyun "uboot=mx31ads/u-boot.bin\0" \ 64*4882a593Smuzhiyun "kernel=mx31ads/uImage\0" \ 65*4882a593Smuzhiyun "nfsroot=/opt/eldk/arm\0" \ 66*4882a593Smuzhiyun "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \ 67*4882a593Smuzhiyun "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs " \ 68*4882a593Smuzhiyun "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ 69*4882a593Smuzhiyun "bootcmd=run bootcmd_net\0" \ 70*4882a593Smuzhiyun "bootcmd_net=run bootargs_base bootargs_nfs; " \ 71*4882a593Smuzhiyun "tftpboot ${loadaddr} ${kernel}; bootm\0" \ 72*4882a593Smuzhiyun "prg_uboot=tftpboot ${loadaddr} ${uboot}; " \ 73*4882a593Smuzhiyun "protect off ${uboot_addr} 0xa003ffff; " \ 74*4882a593Smuzhiyun "erase ${uboot_addr} 0xa003ffff; " \ 75*4882a593Smuzhiyun "cp.b ${loadaddr} ${uboot_addr} ${filesize}; " \ 76*4882a593Smuzhiyun "setenv filesize; saveenv\0" 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun #define CONFIG_CS8900 79*4882a593Smuzhiyun #define CONFIG_CS8900_BASE 0xb4020300 80*4882a593Smuzhiyun #define CONFIG_CS8900_BUS16 1 /* follow the Linux driver */ 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /* 83*4882a593Smuzhiyun * The MX31ADS board seems to have a hardware "peculiarity" confirmed under 84*4882a593Smuzhiyun * U-Boot, RedBoot and Linux: the ethernet Rx signal is reaching the CS8900A 85*4882a593Smuzhiyun * controller inverted. The controller is capable of detecting and correcting 86*4882a593Smuzhiyun * this, but it needs 4 network packets for that. Which means, at startup, you 87*4882a593Smuzhiyun * will not receive answers to the first 4 packest, unless there have been some 88*4882a593Smuzhiyun * broadcasts on the network, or your board is on a hub. Reducing the ARP 89*4882a593Smuzhiyun * timeout from default 5 seconds to 200ms we speed up the initial TFTP 90*4882a593Smuzhiyun * transfer, should the user wish one, significantly. 91*4882a593Smuzhiyun */ 92*4882a593Smuzhiyun #define CONFIG_ARP_TIMEOUT 200UL 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun /* 95*4882a593Smuzhiyun * Miscellaneous configurable options 96*4882a593Smuzhiyun */ 97*4882a593Smuzhiyun #define CONFIG_SYS_LONGHELP /* undef to save memory */ 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ 100*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_END 0x10000 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun #define CONFIG_CMDLINE_EDITING 1 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun /*----------------------------------------------------------------------- 107*4882a593Smuzhiyun * Physical Memory Map 108*4882a593Smuzhiyun */ 109*4882a593Smuzhiyun #define CONFIG_NR_DRAM_BANKS 1 110*4882a593Smuzhiyun #define PHYS_SDRAM_1 CSD0_BASE 111*4882a593Smuzhiyun #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 114*4882a593Smuzhiyun #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 115*4882a593Smuzhiyun #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 116*4882a593Smuzhiyun #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 117*4882a593Smuzhiyun GENERATED_GBL_DATA_SIZE) 118*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 119*4882a593Smuzhiyun CONFIG_SYS_GBL_DATA_OFFSET) 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun /*----------------------------------------------------------------------- 122*4882a593Smuzhiyun * FLASH and environment organization 123*4882a593Smuzhiyun */ 124*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_BASE CS0_BASE 125*4882a593Smuzhiyun #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 126*4882a593Smuzhiyun #define CONFIG_SYS_MAX_FLASH_SECT 262 /* max number of sectors on one chip */ 127*4882a593Smuzhiyun #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */ 128*4882a593Smuzhiyun #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256KiB */ 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun #define CONFIG_ENV_SECT_SIZE (128 * 1024) 131*4882a593Smuzhiyun #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 132*4882a593Smuzhiyun #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun /* Address and size of Redundant Environment Sector */ 135*4882a593Smuzhiyun #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE) 136*4882a593Smuzhiyun #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun /*----------------------------------------------------------------------- 139*4882a593Smuzhiyun * CFI FLASH driver setup 140*4882a593Smuzhiyun */ 141*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */ 142*4882a593Smuzhiyun #define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ 143*4882a593Smuzhiyun #define CONFIG_FLASH_SPANSION_S29WS_N 1 /* A non-standard buffered write algorithm */ 144*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ 145*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */ 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun /* 148*4882a593Smuzhiyun * JFFS2 partitions 149*4882a593Smuzhiyun */ 150*4882a593Smuzhiyun #define CONFIG_JFFS2_DEV "nor0" 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun #endif /* __CONFIG_H */ 153