1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2016 Stefan Roese <sr@denx.de> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _CONFIG_MVEBU_ARMADA_8K_H 8*4882a593Smuzhiyun #define _CONFIG_MVEBU_ARMADA_8K_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* 11*4882a593Smuzhiyun * High Level Configuration Options (easy to change) 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define CONFIG_DISPLAY_BOARDINFO_LATE 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0x00000000 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* additions for new ARM relocation support */ 20*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_BASE 0x00000000 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define CONFIG_NR_DRAM_BANKS 1 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* auto boot */ 25*4882a593Smuzhiyun #define CONFIG_PREBOOT 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ 28*4882a593Smuzhiyun 115200, 230400, 460800, 921600 } 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* 31*4882a593Smuzhiyun * For booting Linux, the board info and command line data 32*4882a593Smuzhiyun * have to be in the first 8 MB of memory, since this is 33*4882a593Smuzhiyun * the maximum mapped by the Linux kernel during initialization. 34*4882a593Smuzhiyun */ 35*4882a593Smuzhiyun #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 36*4882a593Smuzhiyun #define CONFIG_INITRD_TAG /* enable INITRD tag */ 37*4882a593Smuzhiyun #define CONFIG_SETUP_MEMORY_TAGS /* enable memory tag */ 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* 42*4882a593Smuzhiyun * Size of malloc() pool 43*4882a593Smuzhiyun */ 44*4882a593Smuzhiyun #define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MiB for malloc() */ 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* 47*4882a593Smuzhiyun * Other required minimal configurations 48*4882a593Smuzhiyun */ 49*4882a593Smuzhiyun #define CONFIG_SYS_LONGHELP 50*4882a593Smuzhiyun #define CONFIG_AUTO_COMPLETE 51*4882a593Smuzhiyun #define CONFIG_CMDLINE_EDITING 52*4882a593Smuzhiyun #define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ 53*4882a593Smuzhiyun #define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */ 54*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_START 0x00800000 /* 8M */ 55*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_END 0x00ffffff /*(_16M -1) */ 56*4882a593Smuzhiyun #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ 57*4882a593Smuzhiyun #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define CONFIG_SYS_ALT_MEMTEST 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* End of 16M scrubbed by training in bootrom */ 62*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0xFF0000) 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /* 65*4882a593Smuzhiyun * SPI Flash configuration 66*4882a593Smuzhiyun */ 67*4882a593Smuzhiyun #define CONFIG_ENV_SPI_BUS 0 68*4882a593Smuzhiyun #define CONFIG_ENV_SPI_CS 0 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun /* SPI NOR flash default params, used by sf commands */ 71*4882a593Smuzhiyun #define CONFIG_SF_DEFAULT_SPEED 1000000 72*4882a593Smuzhiyun #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 73*4882a593Smuzhiyun #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun /* Environment in SPI NOR flash */ 76*4882a593Smuzhiyun #ifdef CONFIG_MVEBU_SPI_BOOT 77*4882a593Smuzhiyun /* Environment in NAND flash */ 78*4882a593Smuzhiyun #endif 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun #define CONFIG_ENV_OFFSET 0x180000 /* as Marvell U-Boot version */ 81*4882a593Smuzhiyun #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ 82*4882a593Smuzhiyun #define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */ 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun #define CONFIG_SYS_MAX_NAND_DEVICE 1 85*4882a593Smuzhiyun #define CONFIG_SYS_NAND_MAX_CHIPS 1 86*4882a593Smuzhiyun #define CONFIG_SYS_NAND_ONFI_DETECTION 87*4882a593Smuzhiyun #define CONFIG_SYS_NAND_USE_FLASH_BBT 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun /* 90*4882a593Smuzhiyun * Ethernet Driver configuration 91*4882a593Smuzhiyun */ 92*4882a593Smuzhiyun #define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ 93*4882a593Smuzhiyun #define CONFIG_ARP_TIMEOUT 200 94*4882a593Smuzhiyun #define CONFIG_NET_RETRY_COUNT 50 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun #define CONFIG_USB_MAX_CONTROLLER_COUNT (3 + 3) 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun /* USB ethernet */ 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun /* 101*4882a593Smuzhiyun * SATA/SCSI/AHCI configuration 102*4882a593Smuzhiyun */ 103*4882a593Smuzhiyun #define CONFIG_SCSI_AHCI 104*4882a593Smuzhiyun #define CONFIG_SCSI_AHCI_PLAT 105*4882a593Smuzhiyun #define CONFIG_LIBATA 106*4882a593Smuzhiyun #define CONFIG_LBA48 107*4882a593Smuzhiyun #define CONFIG_SYS_64BIT_LBA 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun #define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 110*4882a593Smuzhiyun #define CONFIG_SYS_SCSI_MAX_LUN 1 111*4882a593Smuzhiyun #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 112*4882a593Smuzhiyun CONFIG_SYS_SCSI_MAX_LUN) 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun #define CONFIG_SUPPORT_VFAT 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun /* 117*4882a593Smuzhiyun * PCI configuration 118*4882a593Smuzhiyun */ 119*4882a593Smuzhiyun #ifdef CONFIG_PCIE_DW_MVEBU 120*4882a593Smuzhiyun #define CONFIG_E1000 121*4882a593Smuzhiyun #endif 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun #endif /* _CONFIG_MVEBU_ARMADA_8K_H */ 124