1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Configuation settings for the Hitachi Solution Engine 7750 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __MS7750SE_H 10*4882a593Smuzhiyun #define __MS7750SE_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define CONFIG_CPU_SH7750 1 13*4882a593Smuzhiyun /* #define CONFIG_CPU_SH7751 1 */ 14*4882a593Smuzhiyun /* #define CONFIG_CPU_TYPE_R 1 */ 15*4882a593Smuzhiyun #define CONFIG_MS7750SE 1 16*4882a593Smuzhiyun #define __LITTLE_ENDIAN__ 1 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define CONFIG_DISPLAY_BOARDINFO 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* 21*4882a593Smuzhiyun * Command line configuration. 22*4882a593Smuzhiyun */ 23*4882a593Smuzhiyun #define CONFIG_CONS_SCIF1 1 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define CONFIG_ENV_OVERWRITE 1 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* SDRAM */ 28*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_BASE (0x8C000000) 29*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define CONFIG_SYS_LONGHELP 32*4882a593Smuzhiyun #define CONFIG_SYS_PBSIZE 256 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0x8FFC0000 35*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE) 36*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000) 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* NOR Flash */ 39*4882a593Smuzhiyun /* #define CONFIG_SYS_FLASH_BASE (0xA1000000)*/ 40*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_BASE (0xA0000000) 41*4882a593Smuzhiyun #define CONFIG_SYS_MAX_FLASH_BANKS (1) /* Max number of 42*4882a593Smuzhiyun * Flash memory banks 43*4882a593Smuzhiyun */ 44*4882a593Smuzhiyun #define CONFIG_SYS_MAX_FLASH_SECT 142 45*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024) 48*4882a593Smuzhiyun #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) /* Address of u-boot image in Flash */ 49*4882a593Smuzhiyun #define CONFIG_SYS_MONITOR_LEN (128 * 1024) 50*4882a593Smuzhiyun #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Size of DRAM reserved for malloc() use */ 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 53*4882a593Smuzhiyun #define CONFIG_SYS_RX_ETH_BUFFER (8) 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_CFI 56*4882a593Smuzhiyun #define CONFIG_FLASH_CFI_DRIVER 57*4882a593Smuzhiyun #undef CONFIG_SYS_FLASH_CFI_BROKEN_TABLE 58*4882a593Smuzhiyun #undef CONFIG_SYS_FLASH_QUIET_TEST 59*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #define CONFIG_ENV_SECT_SIZE 0x20000 62*4882a593Smuzhiyun #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) 63*4882a593Smuzhiyun #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 64*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 65*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_WRITE_TOUT 500 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun /* Board Clock */ 68*4882a593Smuzhiyun #define CONFIG_SYS_CLK_FREQ 33333333 69*4882a593Smuzhiyun #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ 70*4882a593Smuzhiyun #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 71*4882a593Smuzhiyun #define CONFIG_SYS_TMU_CLK_DIV 4 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #endif /* __MS7750SE_H */ 74