1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Configuation settings for the Hitachi Solution Engine 7720 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2007 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __MS7720SE_H 10*4882a593Smuzhiyun #define __MS7720SE_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define CONFIG_CPU_SH7720 1 13*4882a593Smuzhiyun #define CONFIG_MS7720SE 1 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define CONFIG_BOOTFILE "/boot/zImage" 16*4882a593Smuzhiyun #define CONFIG_LOADADDR 0x8E000000 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define CONFIG_DISPLAY_BOARDINFO 19*4882a593Smuzhiyun #undef CONFIG_SHOW_BOOT_PROGRESS 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* MEMORY */ 22*4882a593Smuzhiyun #define MS7720SE_SDRAM_BASE 0x8C000000 23*4882a593Smuzhiyun #define MS7720SE_FLASH_BASE_1 0xA0000000 24*4882a593Smuzhiyun #define MS7720SE_FLASH_BANK_SIZE (8 * 1024 * 1024) 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0x8FFC0000 27*4882a593Smuzhiyun #define CONFIG_SYS_LONGHELP /* undef to save memory */ 28*4882a593Smuzhiyun #define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */ 29*4882a593Smuzhiyun /* List of legal baudrate settings for this board */ 30*4882a593Smuzhiyun #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* SCIF */ 33*4882a593Smuzhiyun #define CONFIG_CONS_SCIF0 1 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_START MS7720SE_SDRAM_BASE 36*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024)) 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_BASE MS7720SE_SDRAM_BASE 39*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024) 42*4882a593Smuzhiyun #define CONFIG_SYS_MONITOR_BASE MS7720SE_FLASH_BASE_1 43*4882a593Smuzhiyun #define CONFIG_SYS_MONITOR_LEN (128 * 1024) 44*4882a593Smuzhiyun #define CONFIG_SYS_MALLOC_LEN (256 * 1024) 45*4882a593Smuzhiyun #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* FLASH */ 48*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_CFI 49*4882a593Smuzhiyun #define CONFIG_FLASH_CFI_DRIVER 50*4882a593Smuzhiyun #undef CONFIG_SYS_FLASH_QUIET_TEST 51*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_BASE MS7720SE_FLASH_BASE_1 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #define CONFIG_SYS_MAX_FLASH_SECT 150 56*4882a593Smuzhiyun #define CONFIG_SYS_MAX_FLASH_BANKS 1 57*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define CONFIG_ENV_SECT_SIZE (64 * 1024) 60*4882a593Smuzhiyun #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 61*4882a593Smuzhiyun #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 62*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 63*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_WRITE_TOUT 500 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun /* Board Clock */ 66*4882a593Smuzhiyun #define CONFIG_SYS_CLK_FREQ 33333333 67*4882a593Smuzhiyun #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ 68*4882a593Smuzhiyun #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 69*4882a593Smuzhiyun #define CONFIG_SYS_TMU_CLK_DIV 4 /* 4 (default), 16, 64, 256 or 1024 */ 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* PCMCIA */ 72*4882a593Smuzhiyun #define CONFIG_IDE_PCMCIA 1 73*4882a593Smuzhiyun #define CONFIG_MARUBUN_PCCARD 1 74*4882a593Smuzhiyun #define CONFIG_PCMCIA_SLOT_A 1 75*4882a593Smuzhiyun #define CONFIG_SYS_IDE_MAXDEVICE 1 76*4882a593Smuzhiyun #define CONFIG_SYS_MARUBUN_MRSHPC 0xb83fffe0 77*4882a593Smuzhiyun #define CONFIG_SYS_MARUBUN_MW1 0xb8400000 78*4882a593Smuzhiyun #define CONFIG_SYS_MARUBUN_MW2 0xb8500000 79*4882a593Smuzhiyun #define CONFIG_SYS_MARUBUN_IO 0xb8600000 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun #define CONFIG_SYS_PIO_MODE 1 82*4882a593Smuzhiyun #define CONFIG_SYS_IDE_MAXBUS 1 83*4882a593Smuzhiyun #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_MARUBUN_IO /* base address */ 84*4882a593Smuzhiyun #define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */ 85*4882a593Smuzhiyun #define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */ 86*4882a593Smuzhiyun #define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */ 87*4882a593Smuzhiyun #define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */ 88*4882a593Smuzhiyun #define CONFIG_IDE_SWAP_IO 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun #endif /* __MS7720SE_H */ 91