1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Configuation settings for MPR2 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2008 5*4882a593Smuzhiyun * Mark Jonas <mark.jonas@de.bosch.com> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __MPR2_H 11*4882a593Smuzhiyun #define __MPR2_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* Supported commands */ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* Default environment variables */ 16*4882a593Smuzhiyun #define CONFIG_BOOTFILE "/boot/zImage" 17*4882a593Smuzhiyun #define CONFIG_LOADADDR 0x8E000000 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* CPU and platform */ 20*4882a593Smuzhiyun #define CONFIG_CPU_SH7720 1 21*4882a593Smuzhiyun #define CONFIG_MPR2 1 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define CONFIG_DISPLAY_BOARDINFO 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* U-Boot internals */ 26*4882a593Smuzhiyun #define CONFIG_SYS_LONGHELP /* undef to save memory */ 27*4882a593Smuzhiyun #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate settings for this board */ 28*4882a593Smuzhiyun #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024) 29*4882a593Smuzhiyun #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 30*4882a593Smuzhiyun #define CONFIG_SYS_MONITOR_LEN (128 * 1024) 31*4882a593Smuzhiyun #define CONFIG_SYS_MALLOC_LEN (256 * 1024) 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0x8FFC0000 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* Memory */ 36*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_BASE 0x8C000000 37*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) 38*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 39*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024)) 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* Flash */ 42*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_CFI 43*4882a593Smuzhiyun #define CONFIG_FLASH_CFI_DRIVER 44*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_EMPTY_INFO 45*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_BASE 0xA0000000 46*4882a593Smuzhiyun #define CONFIG_SYS_MAX_FLASH_SECT 256 47*4882a593Smuzhiyun #define CONFIG_SYS_MAX_FLASH_BANKS 1 48*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 49*4882a593Smuzhiyun #define CONFIG_ENV_SECT_SIZE (128 * 1024) 50*4882a593Smuzhiyun #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 51*4882a593Smuzhiyun #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 52*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 53*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_WRITE_TOUT 500 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* Clocks */ 56*4882a593Smuzhiyun #define CONFIG_SYS_CLK_FREQ 24000000 57*4882a593Smuzhiyun #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ 58*4882a593Smuzhiyun #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 59*4882a593Smuzhiyun #define CONFIG_SYS_TMU_CLK_DIV 4 /* 4 (default), 16, 64, 256 or 1024 */ 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* UART */ 62*4882a593Smuzhiyun #define CONFIG_CONS_SCIF0 1 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #endif /* __MPR2_H */ 65