1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2007-2008 3*4882a593Smuzhiyun * Stelian Pop <stelian@popies.net> 4*4882a593Smuzhiyun * Lead Tech Design <www.leadtechdesign.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * (C) Copyright 2009-2015 7*4882a593Smuzhiyun * Daniel Gorsulowski <daniel.gorsulowski@esd.eu> 8*4882a593Smuzhiyun * esd electronic system design gmbh <www.esd.eu> 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * Configuation settings for the esd MEESC board. 11*4882a593Smuzhiyun * 12*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 13*4882a593Smuzhiyun */ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #ifndef __CONFIG_H 16*4882a593Smuzhiyun #define __CONFIG_H 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* 19*4882a593Smuzhiyun * SoC must be defined first, before hardware.h is included. 20*4882a593Smuzhiyun * In this case SoC is defined in boards.cfg. 21*4882a593Smuzhiyun */ 22*4882a593Smuzhiyun #include <asm/hardware.h> 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* 25*4882a593Smuzhiyun * Warning: changing CONFIG_SYS_TEXT_BASE requires 26*4882a593Smuzhiyun * adapting the initial boot program. 27*4882a593Smuzhiyun * Since the linker has to swallow that define, we must use a pure 28*4882a593Smuzhiyun * hex number here! 29*4882a593Smuzhiyun */ 30*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0x21F00000 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* ARM asynchronous clock */ 33*4882a593Smuzhiyun #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* 32.768 kHz crystal */ 34*4882a593Smuzhiyun #define CONFIG_SYS_AT91_MAIN_CLOCK 16000000/* 16.0 MHz crystal */ 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* Misc CPU related */ 37*4882a593Smuzhiyun #define CONFIG_SKIP_LOWLEVEL_INIT 38*4882a593Smuzhiyun #define CONFIG_ARCH_CPU_INIT 39*4882a593Smuzhiyun #define CONFIG_SETUP_MEMORY_TAGS 40*4882a593Smuzhiyun #define CONFIG_INITRD_TAG 41*4882a593Smuzhiyun #define CONFIG_SERIAL_TAG 42*4882a593Smuzhiyun #define CONFIG_REVISION_TAG 43*4882a593Smuzhiyun #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 44*4882a593Smuzhiyun #define CONFIG_MISC_INIT_R /* Call misc_init_r */ 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define CONFIG_PREBOOT /* enable preboot variable */ 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* 49*4882a593Smuzhiyun * Hardware drivers 50*4882a593Smuzhiyun */ 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* 53*4882a593Smuzhiyun * BOOTP options 54*4882a593Smuzhiyun */ 55*4882a593Smuzhiyun #define CONFIG_BOOTP_BOOTFILESIZE 56*4882a593Smuzhiyun #define CONFIG_BOOTP_BOOTPATH 57*4882a593Smuzhiyun #define CONFIG_BOOTP_GATEWAY 58*4882a593Smuzhiyun #define CONFIG_BOOTP_HOSTNAME 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /* 61*4882a593Smuzhiyun * SDRAM: 1 bank, min 32, max 128 MB 62*4882a593Smuzhiyun * Initialized before u-boot gets started. 63*4882a593Smuzhiyun */ 64*4882a593Smuzhiyun #define PHYS_SDRAM ATMEL_BASE_CS1 /* 0x20000000 */ 65*4882a593Smuzhiyun #define PHYS_SDRAM_SIZE 0x02000000 /* 32 MByte */ 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #define CONFIG_NR_DRAM_BANKS 1 68*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM 69*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_SIZE 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x00100000) 72*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01E00000) 73*4882a593Smuzhiyun #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x00100000) 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun /* 76*4882a593Smuzhiyun * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM, 77*4882a593Smuzhiyun * leaving the correct space for initial global data structure above 78*4882a593Smuzhiyun * that address while providing maximum stack area below. 79*4882a593Smuzhiyun */ 80*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_ADDR \ 81*4882a593Smuzhiyun (ATMEL_BASE_SRAM0 + 16 * 1024 - GENERATED_GBL_DATA_SIZE) 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun /* NAND flash */ 84*4882a593Smuzhiyun #ifdef CONFIG_CMD_NAND 85*4882a593Smuzhiyun # define CONFIG_SYS_MAX_NAND_DEVICE 1 86*4882a593Smuzhiyun # define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 /* 0x40000000 */ 87*4882a593Smuzhiyun # define CONFIG_SYS_NAND_DBW_8 88*4882a593Smuzhiyun # define CONFIG_SYS_NAND_MASK_ALE (1 << 21) 89*4882a593Smuzhiyun # define CONFIG_SYS_NAND_MASK_CLE (1 << 22) 90*4882a593Smuzhiyun # define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15) 91*4882a593Smuzhiyun # define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PA(22) 92*4882a593Smuzhiyun #endif 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun /* Ethernet */ 95*4882a593Smuzhiyun #define CONFIG_MACB 96*4882a593Smuzhiyun #define CONFIG_RMII 97*4882a593Smuzhiyun #define CONFIG_NET_RETRY_COUNT 20 98*4882a593Smuzhiyun #undef CONFIG_RESET_PHY_R 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun /* hw-controller addresses */ 101*4882a593Smuzhiyun #define CONFIG_ET1100_BASE 0x70000000 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun #ifdef CONFIG_SYS_USE_DATAFLASH 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun /* bootstrap + u-boot + env in dataflash on CS0 */ 106*4882a593Smuzhiyun #define CONFIG_ENV_OFFSET 0x4200 107*4882a593Smuzhiyun #define CONFIG_ENV_SIZE 0x4200 108*4882a593Smuzhiyun #define CONFIG_ENV_SECT_SIZE 0x210 109*4882a593Smuzhiyun #define CONFIG_ENV_SPI_MAX_HZ 15000000 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun #elif CONFIG_SYS_USE_NANDFLASH 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun /* bootstrap + u-boot + env + linux in nandflash */ 114*4882a593Smuzhiyun # define CONFIG_ENV_OFFSET 0xC0000 115*4882a593Smuzhiyun # define CONFIG_ENV_SIZE 0x20000 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun #endif 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun #define CONFIG_SYS_CBSIZE 512 120*4882a593Smuzhiyun #define CONFIG_SYS_LONGHELP 121*4882a593Smuzhiyun #define CONFIG_CMDLINE_EDITING 122*4882a593Smuzhiyun #define CONFIG_AUTO_COMPLETE 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun /* 125*4882a593Smuzhiyun * Size of malloc() pool 126*4882a593Smuzhiyun */ 127*4882a593Smuzhiyun #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + \ 128*4882a593Smuzhiyun 128*1024, 0x1000) 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun #endif 131