1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2014 Stefan Roese <sr@denx.de> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _CONFIG_DB_MV7846MP_GP_H 8*4882a593Smuzhiyun #define _CONFIG_DB_MV7846MP_GP_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* 11*4882a593Smuzhiyun * High Level Configuration Options (easy to change) 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun #define CONFIG_DISPLAY_BOARDINFO_LATE 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* 16*4882a593Smuzhiyun * TEXT_BASE needs to be below 16MiB, since this area is scrubbed 17*4882a593Smuzhiyun * for DDR ECC byte filling in the SPL before loading the main 18*4882a593Smuzhiyun * U-Boot into it. 19*4882a593Smuzhiyun */ 20*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0x00800000 21*4882a593Smuzhiyun #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun /* 24*4882a593Smuzhiyun * Commands configuration 25*4882a593Smuzhiyun */ 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* I2C */ 28*4882a593Smuzhiyun #define CONFIG_SYS_I2C 29*4882a593Smuzhiyun #define CONFIG_SYS_I2C_MVTWSI 30*4882a593Smuzhiyun #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE 31*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SLAVE 0x0 32*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SPEED 100000 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* SPI NOR flash default params, used by sf commands */ 35*4882a593Smuzhiyun #define CONFIG_SF_DEFAULT_SPEED 1000000 36*4882a593Smuzhiyun #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* Environment in SPI NOR flash */ 39*4882a593Smuzhiyun #define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ 40*4882a593Smuzhiyun #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ 41*4882a593Smuzhiyun #define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */ 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define CONFIG_PHY_MARVELL /* there is a marvell phy */ 44*4882a593Smuzhiyun #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define CONFIG_SYS_ALT_MEMTEST 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* 49*4882a593Smuzhiyun * mv-common.h should be defined after CMD configs since it used them 50*4882a593Smuzhiyun * to enable certain macros 51*4882a593Smuzhiyun */ 52*4882a593Smuzhiyun #include "mv-common.h" 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* 55*4882a593Smuzhiyun * Memory layout while starting into the bin_hdr via the 56*4882a593Smuzhiyun * BootROM: 57*4882a593Smuzhiyun * 58*4882a593Smuzhiyun * 0x4000.4000 - 0x4003.4000 headers space (192KiB) 59*4882a593Smuzhiyun * 0x4000.4030 bin_hdr start address 60*4882a593Smuzhiyun * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) 61*4882a593Smuzhiyun * 0x4007.fffc BootROM stack top 62*4882a593Smuzhiyun * 63*4882a593Smuzhiyun * The address space between 0x4007.fffc and 0x400f.fff is not locked in 64*4882a593Smuzhiyun * L2 cache thus cannot be used. 65*4882a593Smuzhiyun */ 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun /* SPL */ 68*4882a593Smuzhiyun /* Defines for SPL */ 69*4882a593Smuzhiyun #define CONFIG_SPL_FRAMEWORK 70*4882a593Smuzhiyun #define CONFIG_SPL_TEXT_BASE 0x40004030 71*4882a593Smuzhiyun #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) 74*4882a593Smuzhiyun #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #ifdef CONFIG_SPL_BUILD 77*4882a593Smuzhiyun #define CONFIG_SYS_MALLOC_SIMPLE 78*4882a593Smuzhiyun #endif 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) 81*4882a593Smuzhiyun #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun /* SPL related SPI defines */ 84*4882a593Smuzhiyun #define CONFIG_SPL_SPI_LOAD 85*4882a593Smuzhiyun #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ 88*4882a593Smuzhiyun #define CONFIG_DDR_FIXED_SIZE (1 << 20) /* 1GiB */ 89*4882a593Smuzhiyun #define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */ 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun #endif /* _CONFIG_DB_MV7846MP_GP_H */ 92