1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2014 Freescale Semiconductor 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __LS2_EMU_H 8*4882a593Smuzhiyun #define __LS2_EMU_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include "ls2080a_common.h" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define CONFIG_SYS_CLK_FREQ 100000000 13*4882a593Smuzhiyun #define CONFIG_DDR_CLK_FREQ 133333333 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define CONFIG_SYS_MXC_I2C1_SPEED 40000000 16*4882a593Smuzhiyun #define CONFIG_SYS_MXC_I2C2_SPEED 40000000 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define CONFIG_DDR_SPD 19*4882a593Smuzhiyun #define CONFIG_SYS_FSL_DDR_EMU /* Support emulator */ 20*4882a593Smuzhiyun #define SPD_EEPROM_ADDRESS1 0x51 21*4882a593Smuzhiyun #define SPD_EEPROM_ADDRESS2 0x52 22*4882a593Smuzhiyun #define SPD_EEPROM_ADDRESS3 0x53 23*4882a593Smuzhiyun #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 24*4882a593Smuzhiyun #define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD on I2C bus 1 */ 25*4882a593Smuzhiyun #define CONFIG_DIMM_SLOTS_PER_CTLR 1 26*4882a593Smuzhiyun #define CONFIG_CHIP_SELECTS_PER_CTRL 4 27*4882a593Smuzhiyun #ifdef CONFIG_SYS_FSL_HAS_DP_DDR 28*4882a593Smuzhiyun #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 29*4882a593Smuzhiyun #endif 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define CONFIG_FSL_DDR_SYNC_REFRESH 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 34*4882a593Smuzhiyun #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 35*4882a593Smuzhiyun /* 36*4882a593Smuzhiyun * NOR Flash Timing Params 37*4882a593Smuzhiyun */ 38*4882a593Smuzhiyun #define CONFIG_SYS_NOR0_CSPR \ 39*4882a593Smuzhiyun (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 40*4882a593Smuzhiyun CSPR_PORT_SIZE_16 | \ 41*4882a593Smuzhiyun CSPR_MSEL_NOR | \ 42*4882a593Smuzhiyun CSPR_V) 43*4882a593Smuzhiyun #define CONFIG_SYS_NOR0_CSPR_EARLY \ 44*4882a593Smuzhiyun (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ 45*4882a593Smuzhiyun CSPR_PORT_SIZE_16 | \ 46*4882a593Smuzhiyun CSPR_MSEL_NOR | \ 47*4882a593Smuzhiyun CSPR_V) 48*4882a593Smuzhiyun #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) 49*4882a593Smuzhiyun #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ 50*4882a593Smuzhiyun FTIM0_NOR_TEADC(0x1) | \ 51*4882a593Smuzhiyun FTIM0_NOR_TEAHC(0x1)) 52*4882a593Smuzhiyun #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \ 53*4882a593Smuzhiyun FTIM1_NOR_TRAD_NOR(0x1)) 54*4882a593Smuzhiyun #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \ 55*4882a593Smuzhiyun FTIM2_NOR_TCH(0x0) | \ 56*4882a593Smuzhiyun FTIM2_NOR_TWP(0x1)) 57*4882a593Smuzhiyun #define CONFIG_SYS_NOR_FTIM3 0x04000000 58*4882a593Smuzhiyun #define CONFIG_SYS_IFC_CCR 0x01000000 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 61*4882a593Smuzhiyun #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY 62*4882a593Smuzhiyun #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR 63*4882a593Smuzhiyun #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 64*4882a593Smuzhiyun #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 65*4882a593Smuzhiyun #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 66*4882a593Smuzhiyun #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 67*4882a593Smuzhiyun #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 68*4882a593Smuzhiyun #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun /* Debug Server firmware */ 71*4882a593Smuzhiyun #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR 72*4882a593Smuzhiyun #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580C00000ULL 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun /* 75*4882a593Smuzhiyun * This trick allows users to load MC images into DDR directly without 76*4882a593Smuzhiyun * copying from NOR flash. It dramatically improves speed. 77*4882a593Smuzhiyun */ 78*4882a593Smuzhiyun #define CONFIG_SYS_LS_MC_FW_IN_DDR 79*4882a593Smuzhiyun #define CONFIG_SYS_LS_MC_DPL_IN_DDR 80*4882a593Smuzhiyun #define CONFIG_SYS_LS_MC_DPC_IN_DDR 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 200000 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun /* Store environment at top of flash */ 85*4882a593Smuzhiyun #define CONFIG_ENV_SIZE 0x1000 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun #endif /* __LS2_EMU_H */ 88