1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2016 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __LS1012AQDS_H__ 8*4882a593Smuzhiyun #define __LS1012AQDS_H__ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include "ls1012a_common.h" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* DDR */ 13*4882a593Smuzhiyun #define CONFIG_DIMM_SLOTS_PER_CTLR 1 14*4882a593Smuzhiyun #define CONFIG_CHIP_SELECTS_PER_CTRL 1 15*4882a593Smuzhiyun #define CONFIG_NR_DRAM_BANKS 2 16*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_SIZE 0x40000000 17*4882a593Smuzhiyun #define CONFIG_CMD_MEMINFO 18*4882a593Smuzhiyun #define CONFIG_CMD_MEMTEST 19*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_START 0x80000000 20*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_END 0x9fffffff 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* 23*4882a593Smuzhiyun * QIXIS Definitions 24*4882a593Smuzhiyun */ 25*4882a593Smuzhiyun #define CONFIG_FSL_QIXIS 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #ifdef CONFIG_FSL_QIXIS 28*4882a593Smuzhiyun #define CONFIG_QIXIS_I2C_ACCESS 29*4882a593Smuzhiyun #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 30*4882a593Smuzhiyun #define QIXIS_LBMAP_BRDCFG_REG 0x04 31*4882a593Smuzhiyun #define QIXIS_LBMAP_SWITCH 6 32*4882a593Smuzhiyun #define QIXIS_LBMAP_MASK 0x08 33*4882a593Smuzhiyun #define QIXIS_LBMAP_SHIFT 0 34*4882a593Smuzhiyun #define QIXIS_LBMAP_DFLTBANK 0x00 35*4882a593Smuzhiyun #define QIXIS_LBMAP_ALTBANK 0x08 36*4882a593Smuzhiyun #define QIXIS_RST_CTL_RESET 0x31 37*4882a593Smuzhiyun #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 38*4882a593Smuzhiyun #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 39*4882a593Smuzhiyun #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 40*4882a593Smuzhiyun #endif 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* 43*4882a593Smuzhiyun * I2C bus multiplexer 44*4882a593Smuzhiyun */ 45*4882a593Smuzhiyun #define I2C_MUX_PCA_ADDR_PRI 0x77 46*4882a593Smuzhiyun #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 47*4882a593Smuzhiyun #define I2C_RETIMER_ADDR 0x18 48*4882a593Smuzhiyun #define I2C_MUX_CH_DEFAULT 0x8 49*4882a593Smuzhiyun #define I2C_MUX_CH_CH7301 0xC 50*4882a593Smuzhiyun #define I2C_MUX_CH5 0xD 51*4882a593Smuzhiyun #define I2C_MUX_CH7 0xF 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define I2C_MUX_CH_VOL_MONITOR 0xa 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* 56*4882a593Smuzhiyun * RTC configuration 57*4882a593Smuzhiyun */ 58*4882a593Smuzhiyun #define RTC 59*4882a593Smuzhiyun #define CONFIG_RTC_PCF8563 1 60*4882a593Smuzhiyun #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun /* EEPROM */ 63*4882a593Smuzhiyun #define CONFIG_ID_EEPROM 64*4882a593Smuzhiyun #define CONFIG_SYS_I2C_EEPROM_NXID 65*4882a593Smuzhiyun #define CONFIG_SYS_EEPROM_BUS_NUM 0 66*4882a593Smuzhiyun #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 67*4882a593Smuzhiyun #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 68*4882a593Smuzhiyun #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 69*4882a593Smuzhiyun #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* Voltage monitor on channel 2*/ 73*4882a593Smuzhiyun #define I2C_VOL_MONITOR_ADDR 0x40 74*4882a593Smuzhiyun #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 75*4882a593Smuzhiyun #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 76*4882a593Smuzhiyun #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun /* DSPI */ 79*4882a593Smuzhiyun #define CONFIG_FSL_DSPI1 80*4882a593Smuzhiyun #define CONFIG_DEFAULT_SPI_BUS 1 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun #define CONFIG_CMD_SPI 83*4882a593Smuzhiyun #define MMAP_DSPI DSPI1_BASE_ADDR 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun #define CONFIG_SYS_DSPI_CTAR0 1 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun #define CONFIG_SYS_DSPI_CTAR1 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\ 88*4882a593Smuzhiyun DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \ 89*4882a593Smuzhiyun DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \ 90*4882a593Smuzhiyun DSPI_CTAR_DT(0)) 91*4882a593Smuzhiyun #define CONFIG_SPI_FLASH_SST /* cs1 */ 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun #define CONFIG_SYS_DSPI_CTAR2 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\ 94*4882a593Smuzhiyun DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \ 95*4882a593Smuzhiyun DSPI_CTAR_CSSCK(0) | DSPI_CTAR_ASC(0) | \ 96*4882a593Smuzhiyun DSPI_CTAR_DT(0)) 97*4882a593Smuzhiyun #define CONFIG_SPI_FLASH_STMICRO /* cs2 */ 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun #define CONFIG_SYS_DSPI_CTAR3 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\ 100*4882a593Smuzhiyun DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \ 101*4882a593Smuzhiyun DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \ 102*4882a593Smuzhiyun DSPI_CTAR_DT(0)) 103*4882a593Smuzhiyun #define CONFIG_SPI_FLASH_EON /* cs3 */ 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun #define CONFIG_SF_DEFAULT_SPEED 10000000 106*4882a593Smuzhiyun #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 107*4882a593Smuzhiyun #define CONFIG_SF_DEFAULT_BUS 1 108*4882a593Smuzhiyun #define CONFIG_SF_DEFAULT_CS 0 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun /* 111*4882a593Smuzhiyun * USB 112*4882a593Smuzhiyun */ 113*4882a593Smuzhiyun /* EHCI Support - disbaled by default */ 114*4882a593Smuzhiyun /*#define CONFIG_HAS_FSL_DR_USB*/ 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun #ifdef CONFIG_HAS_FSL_DR_USB 117*4882a593Smuzhiyun #define CONFIG_USB_EHCI_FSL 118*4882a593Smuzhiyun #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 119*4882a593Smuzhiyun #endif 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun /*XHCI Support - enabled by default*/ 122*4882a593Smuzhiyun #define CONFIG_HAS_FSL_XHCI_USB 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun #ifdef CONFIG_HAS_FSL_XHCI_USB 125*4882a593Smuzhiyun #define CONFIG_USB_XHCI_FSL 126*4882a593Smuzhiyun #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 127*4882a593Smuzhiyun #endif 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun /* MMC */ 130*4882a593Smuzhiyun #ifdef CONFIG_MMC 131*4882a593Smuzhiyun #define CONFIG_FSL_ESDHC 132*4882a593Smuzhiyun #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 133*4882a593Smuzhiyun #endif 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun /* SATA */ 136*4882a593Smuzhiyun #define CONFIG_LIBATA 137*4882a593Smuzhiyun #define CONFIG_SCSI_AHCI 138*4882a593Smuzhiyun #define CONFIG_SCSI_AHCI_PLAT 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun #define CONFIG_SYS_SATA AHCI_BASE_ADDR 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 143*4882a593Smuzhiyun #define CONFIG_SYS_SCSI_MAX_LUN 1 144*4882a593Smuzhiyun #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 145*4882a593Smuzhiyun CONFIG_SYS_SCSI_MAX_LUN) 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun #define CONFIG_PCIE1 /* PCIE controller 1 */ 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun #define CONFIG_NET_MULTI 150*4882a593Smuzhiyun #define CONFIG_PCI_SCAN_SHOW 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun #define CONFIG_CMD_MEMINFO 153*4882a593Smuzhiyun #define CONFIG_CMD_MEMTEST 154*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_START 0x80000000 155*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_END 0x9fffffff 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun #define CONFIG_MISC_INIT_R 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun #endif /* __LS1012AQDS_H__ */ 160