1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2016 Freescale Semiconductor 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __LS1012A_COMMON_H 8*4882a593Smuzhiyun #define __LS1012A_COMMON_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define CONFIG_FSL_LAYERSCAPE 11*4882a593Smuzhiyun #define CONFIG_GICV2 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include <asm/arch/config.h> 14*4882a593Smuzhiyun #include <asm/arch/stream_id_lsch2.h> 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define CONFIG_SUPPORT_RAW_INITRD 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define CONFIG_DISPLAY_BOARDINFO_LATE 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0x40100000 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define CONFIG_SYS_CLK_FREQ 125000000 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define CONFIG_SKIP_LOWLEVEL_INIT 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) 27*4882a593Smuzhiyun #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 30*4882a593Smuzhiyun #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 31*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 32*4882a593Smuzhiyun #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* Generic Timer Definitions */ 35*4882a593Smuzhiyun #define COUNTER_FREQUENCY CONFIG_SYS_CLK_FREQ/4 /* 25MHz */ 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* CSU */ 38*4882a593Smuzhiyun #define CONFIG_LAYERSCAPE_NS_ACCESS 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* Size of malloc() pool */ 41*4882a593Smuzhiyun #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /*SPI device */ 44*4882a593Smuzhiyun #ifdef CONFIG_QSPI_BOOT 45*4882a593Smuzhiyun #define CONFIG_SYS_QE_FW_IN_SPIFLASH 46*4882a593Smuzhiyun #define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000 47*4882a593Smuzhiyun #define CONFIG_ENV_SPI_BUS 0 48*4882a593Smuzhiyun #define CONFIG_ENV_SPI_CS 0 49*4882a593Smuzhiyun #define CONFIG_ENV_SPI_MAX_HZ 1000000 50*4882a593Smuzhiyun #define CONFIG_ENV_SPI_MODE 0x03 51*4882a593Smuzhiyun #define CONFIG_SPI_FLASH_SPANSION 52*4882a593Smuzhiyun #define CONFIG_FSL_SPI_INTERFACE 53*4882a593Smuzhiyun #define CONFIG_SF_DATAFLASH 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #define CONFIG_FSL_QSPI 56*4882a593Smuzhiyun #define QSPI0_AMBA_BASE 0x40000000 57*4882a593Smuzhiyun #define CONFIG_SPI_FLASH_SPANSION 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define FSL_QSPI_FLASH_SIZE SZ_64M 60*4882a593Smuzhiyun #define FSL_QSPI_FLASH_NUM 2 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun /* 63*4882a593Smuzhiyun * Environment 64*4882a593Smuzhiyun */ 65*4882a593Smuzhiyun #define CONFIG_ENV_OVERWRITE 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #define CONFIG_ENV_SIZE 0x40000 /* 256KB */ 68*4882a593Smuzhiyun #define CONFIG_ENV_OFFSET 0x200000 /* 2MB */ 69*4882a593Smuzhiyun #define CONFIG_ENV_SECT_SIZE 0x40000 70*4882a593Smuzhiyun #endif 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* I2C */ 73*4882a593Smuzhiyun #define CONFIG_SYS_I2C 74*4882a593Smuzhiyun #define CONFIG_SYS_I2C_MXC 75*4882a593Smuzhiyun #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 76*4882a593Smuzhiyun #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun #define CONFIG_CONS_INDEX 1 79*4882a593Smuzhiyun #define CONFIG_SYS_NS16550_SERIAL 80*4882a593Smuzhiyun #define CONFIG_SYS_NS16550_REG_SIZE 1 81*4882a593Smuzhiyun #define CONFIG_SYS_NS16550_CLK (get_serial_clock()) 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun /* Command line configuration */ 86*4882a593Smuzhiyun #undef CONFIG_CMD_IMLS 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun #define CONFIG_SYS_HZ 1000 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun #define CONFIG_HWCONFIG 91*4882a593Smuzhiyun #define HWCONFIG_BUFFER_SIZE 128 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun /* Initial environment variables */ 94*4882a593Smuzhiyun #define CONFIG_EXTRA_ENV_SETTINGS \ 95*4882a593Smuzhiyun "verify=no\0" \ 96*4882a593Smuzhiyun "loadaddr=0x80100000\0" \ 97*4882a593Smuzhiyun "kernel_addr=0x100000\0" \ 98*4882a593Smuzhiyun "fdt_high=0xffffffffffffffff\0" \ 99*4882a593Smuzhiyun "initrd_high=0xffffffffffffffff\0" \ 100*4882a593Smuzhiyun "kernel_start=0xa00000\0" \ 101*4882a593Smuzhiyun "kernel_load=0xa0000000\0" \ 102*4882a593Smuzhiyun "kernel_size=0x2800000\0" \ 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun #define CONFIG_BOOTCOMMAND "sf probe 0:0; sf read $kernel_load "\ 105*4882a593Smuzhiyun "$kernel_start $kernel_size && "\ 106*4882a593Smuzhiyun "bootm $kernel_load" 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun /* Monitor Command Prompt */ 109*4882a593Smuzhiyun #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 110*4882a593Smuzhiyun #define CONFIG_SYS_LONGHELP 111*4882a593Smuzhiyun #define CONFIG_CMDLINE_EDITING 1 112*4882a593Smuzhiyun #define CONFIG_AUTO_COMPLETE 113*4882a593Smuzhiyun #define CONFIG_SYS_MAXARGS 64 /* max command args */ 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun #include <asm/arch/soc.h> 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun #endif /* __LS1012A_COMMON_H */ 120