1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * include/configs/lager.h 3*4882a593Smuzhiyun * This file is lager board configuration. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2013, 2014 Renesas Electronics Corporation 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __LAGER_H 11*4882a593Smuzhiyun #define __LAGER_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #undef DEBUG 14*4882a593Smuzhiyun #define CONFIG_R8A7790 15*4882a593Smuzhiyun #define CONFIG_ARCH_RMOBILE_BOARD_STRING "Lager" 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #include "rcar-gen2-common.h" 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT) 20*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0xB0000000 21*4882a593Smuzhiyun #else 22*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0xE8080000 23*4882a593Smuzhiyun #endif 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* STACK */ 26*4882a593Smuzhiyun #if defined(CONFIGF_RMOBILE_EXTRAM_BOOT) 27*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_ADDR 0xB003FFFC 28*4882a593Smuzhiyun #else 29*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_ADDR 0xE827FFFC 30*4882a593Smuzhiyun #endif 31*4882a593Smuzhiyun #define STACK_AREA_SIZE 0xC000 32*4882a593Smuzhiyun #define LOW_LEVEL_MERAM_STACK \ 33*4882a593Smuzhiyun (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* MEMORY */ 36*4882a593Smuzhiyun #define RCAR_GEN2_SDRAM_BASE 0x40000000 37*4882a593Smuzhiyun #define RCAR_GEN2_SDRAM_SIZE (2048u * 1024 * 1024) 38*4882a593Smuzhiyun #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* SCIF */ 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* SPI */ 43*4882a593Smuzhiyun #define CONFIG_SPI 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* SH Ether */ 46*4882a593Smuzhiyun #define CONFIG_SH_ETHER 47*4882a593Smuzhiyun #define CONFIG_SH_ETHER_USE_PORT 0 48*4882a593Smuzhiyun #define CONFIG_SH_ETHER_PHY_ADDR 0x1 49*4882a593Smuzhiyun #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII 50*4882a593Smuzhiyun #define CONFIG_SH_ETHER_ALIGNE_SIZE 64 51*4882a593Smuzhiyun #define CONFIG_SH_ETHER_CACHE_WRITEBACK 52*4882a593Smuzhiyun #define CONFIG_SH_ETHER_CACHE_INVALIDATE 53*4882a593Smuzhiyun #define CONFIG_BITBANGMII 54*4882a593Smuzhiyun #define CONFIG_BITBANGMII_MULTI 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* I2C */ 57*4882a593Smuzhiyun #define CONFIG_SYS_I2C 58*4882a593Smuzhiyun #define CONFIG_SYS_I2C_RCAR 59*4882a593Smuzhiyun #define CONFIG_SYS_RCAR_I2C0_SPEED 400000 60*4882a593Smuzhiyun #define CONFIG_SYS_RCAR_I2C1_SPEED 400000 61*4882a593Smuzhiyun #define CONFIG_SYS_RCAR_I2C2_SPEED 400000 62*4882a593Smuzhiyun #define CONFIG_SYS_RCAR_I2C3_SPEED 400000 63*4882a593Smuzhiyun #define CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS 4 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */ 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun /* Board Clock */ 68*4882a593Smuzhiyun #define RMOBILE_XTAL_CLK 20000000u 69*4882a593Smuzhiyun #define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK 70*4882a593Smuzhiyun #define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */ 71*4882a593Smuzhiyun #define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2) 72*4882a593Smuzhiyun #define CONFIG_PLL1_DIV2_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 2) 73*4882a593Smuzhiyun #define CONFIG_MP_CLK_FREQ (CONFIG_PLL1_DIV2_CLK_FREQ / 15) 74*4882a593Smuzhiyun #define CONFIG_HP_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 12) 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #define CONFIG_SYS_TMU_CLK_DIV 4 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun /* USB */ 79*4882a593Smuzhiyun #define CONFIG_USB_EHCI_RMOBILE 80*4882a593Smuzhiyun #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /* MMC */ 83*4882a593Smuzhiyun #define CONFIG_SH_MMCIF 84*4882a593Smuzhiyun #define CONFIG_SH_MMCIF_ADDR 0xEE220000 85*4882a593Smuzhiyun #define CONFIG_SH_MMCIF_CLK 97500000 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun /* Module stop status bits */ 88*4882a593Smuzhiyun /* INTC-RT */ 89*4882a593Smuzhiyun #define CONFIG_SMSTP0_ENA 0x00400000 90*4882a593Smuzhiyun /* MSIF */ 91*4882a593Smuzhiyun #define CONFIG_SMSTP2_ENA 0x00002000 92*4882a593Smuzhiyun /* INTC-SYS, IRQC */ 93*4882a593Smuzhiyun #define CONFIG_SMSTP4_ENA 0x00000180 94*4882a593Smuzhiyun /* SCIF0 */ 95*4882a593Smuzhiyun #define CONFIG_SMSTP7_ENA 0x00200000 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun /* SDHI */ 98*4882a593Smuzhiyun #define CONFIG_SH_SDHI_FREQ 97500000 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun #endif /* __LAGER_H */ 101