1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> 3*4882a593Smuzhiyun * Copyright (C) 2012 Renesas Solutions Corp. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __KZM9G_H 9*4882a593Smuzhiyun #define __KZM9G_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #undef DEBUG 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define CONFIG_SH73A0 14*4882a593Smuzhiyun #define CONFIG_KZM_A9_GT 15*4882a593Smuzhiyun #define CONFIG_ARCH_RMOBILE_BOARD_STRING "KMC KZM-A9-GT" 16*4882a593Smuzhiyun #define CONFIG_MACH_TYPE MACH_TYPE_KZM9G 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #include <asm/arch/rmobile.h> 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define CONFIG_ARCH_CPU_INIT 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define CONFIG_CMDLINE_TAG 23*4882a593Smuzhiyun #define CONFIG_SETUP_MEMORY_TAGS 24*4882a593Smuzhiyun #define CONFIG_INITRD_TAG 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #undef CONFIG_SHOW_BOOT_PROGRESS 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* MEMORY */ 29*4882a593Smuzhiyun #define KZM_SDRAM_BASE (0x40000000) 30*4882a593Smuzhiyun #define PHYS_SDRAM KZM_SDRAM_BASE 31*4882a593Smuzhiyun #define PHYS_SDRAM_SIZE (512 * 1024 * 1024) 32*4882a593Smuzhiyun #define CONFIG_NR_DRAM_BANKS (1) 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* NOR Flash */ 35*4882a593Smuzhiyun #define KZM_FLASH_BASE (0x00000000) 36*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_BASE (KZM_FLASH_BASE) 37*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_CFI_WIDTH (FLASH_CFI_16BIT) 38*4882a593Smuzhiyun #define CONFIG_SYS_MAX_FLASH_BANKS (1) 39*4882a593Smuzhiyun #define CONFIG_SYS_MAX_FLASH_SECT (512) 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* prompt */ 42*4882a593Smuzhiyun #define CONFIG_SYS_LONGHELP 43*4882a593Smuzhiyun #define CONFIG_SYS_PBSIZE 256 44*4882a593Smuzhiyun #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* SCIF */ 47*4882a593Smuzhiyun #define CONFIG_CONS_SCIF4 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_START (KZM_SDRAM_BASE) 50*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_END \ 51*4882a593Smuzhiyun (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024)) 52*4882a593Smuzhiyun #undef CONFIG_SYS_ALT_MEMTEST 53*4882a593Smuzhiyun #undef CONFIG_SYS_MEMTEST_SCRATCH 54*4882a593Smuzhiyun #undef CONFIG_SYS_LOADS_BAUD_CHANGE 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #define CONFIG_SYS_INIT_RAM_ADDR (0xE5600000) /* on MERAM */ 57*4882a593Smuzhiyun #define CONFIG_SYS_INIT_RAM_SIZE (0x10000) 58*4882a593Smuzhiyun #define LOW_LEVEL_MERAM_STACK (CONFIG_SYS_INIT_RAM_ADDR - 4) 59*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 60*4882a593Smuzhiyun CONFIG_SYS_INIT_RAM_SIZE - \ 61*4882a593Smuzhiyun GENERATED_GBL_DATA_SIZE) 62*4882a593Smuzhiyun #define CONFIG_SDRAM_OFFSET_FOR_RT (16 * 1024 * 1024) 63*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_BASE (KZM_SDRAM_BASE + CONFIG_SDRAM_OFFSET_FOR_RT) 64*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_SIZE (PHYS_SDRAM_SIZE - CONFIG_SDRAM_OFFSET_FOR_RT) 65*4882a593Smuzhiyun #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024) 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #define CONFIG_SYS_MONITOR_BASE (KZM_FLASH_BASE) 68*4882a593Smuzhiyun #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) 69*4882a593Smuzhiyun #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0x00000000 72*4882a593Smuzhiyun #define CONFIG_STANDALONE_LOAD_ADDR 0x41000000 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun /* FLASH */ 75*4882a593Smuzhiyun #define CONFIG_FLASH_CFI_DRIVER 76*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_CFI 77*4882a593Smuzhiyun #undef CONFIG_SYS_FLASH_QUIET_TEST 78*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_EMPTY_INFO 79*4882a593Smuzhiyun #define FLASH_SECTOR_SIZE (256 * 1024) /* 256 KB sectors */ 80*4882a593Smuzhiyun #define CONFIG_ENV_SIZE FLASH_SECTOR_SIZE 81*4882a593Smuzhiyun #define CONFIG_ENV_OFFSET FLASH_SECTOR_SIZE 82*4882a593Smuzhiyun #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun /* Timeout for Flash erase operations (in ms) */ 85*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) 86*4882a593Smuzhiyun /* Timeout for Flash write operations (in ms) */ 87*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) 88*4882a593Smuzhiyun /* Timeout for Flash set sector lock bit operations (in ms) */ 89*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) 90*4882a593Smuzhiyun /* Timeout for Flash clear lock bit operations (in ms) */ 91*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun #undef CONFIG_SYS_FLASH_PROTECTION 94*4882a593Smuzhiyun #undef CONFIG_SYS_DIRECT_FLASH_TFTP 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun /* GPIO / PFC */ 97*4882a593Smuzhiyun #define CONFIG_SH_GPIO_PFC 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun /* Clock */ 100*4882a593Smuzhiyun #define CONFIG_GLOBAL_TIMER 101*4882a593Smuzhiyun #define CONFIG_SYS_CLK_FREQ (48000000) 102*4882a593Smuzhiyun #define CONFIG_SYS_CPU_CLK (1196000000) 103*4882a593Smuzhiyun #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 104*4882a593Smuzhiyun #define TMU_CLK_DIVIDER (4) /* 4 (default), 16, 64, 256 or 1024 */ 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun /* Ether */ 107*4882a593Smuzhiyun #define CONFIG_SMC911X 108*4882a593Smuzhiyun #define CONFIG_SMC911X_BASE (0x10000000) 109*4882a593Smuzhiyun #define CONFIG_SMC911X_32_BIT 110*4882a593Smuzhiyun #define CONFIG_NFS_TIMEOUT 10000UL 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun /* I2C */ 113*4882a593Smuzhiyun #define CONFIG_SYS_I2C 114*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SH 115*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 5 116*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SH_BASE0 0xE6820000 117*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SH_SPEED0 100000 118*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SH_BASE1 0xE6822000 119*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SH_SPEED1 100000 120*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SH_BASE2 0xE6824000 121*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SH_SPEED2 100000 122*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SH_BASE3 0xE6826000 123*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SH_SPEED3 100000 124*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SH_BASE4 0xE6828000 125*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SH_SPEED4 100000 126*4882a593Smuzhiyun #define CONFIG_SH_I2C_8BIT 127*4882a593Smuzhiyun #define CONFIG_SH_I2C_DATA_HIGH 4 128*4882a593Smuzhiyun #define CONFIG_SH_I2C_DATA_LOW 5 129*4882a593Smuzhiyun #define CONFIG_SH_I2C_CLOCK 104000000 /* 104 MHz */ 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun #endif /* __KZM9G_H */ 132