1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2009 3*4882a593Smuzhiyun * Marvell Semiconductor <www.marvell.com> 4*4882a593Smuzhiyun * Prafulla Wadaskar <prafulla@marvell.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * (C) Copyright 2009 7*4882a593Smuzhiyun * Stefan Roese, DENX Software Engineering, sr@denx.de. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * (C) Copyright 2011-2012 10*4882a593Smuzhiyun * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com 11*4882a593Smuzhiyun * Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com 12*4882a593Smuzhiyun * 13*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 14*4882a593Smuzhiyun */ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* 17*4882a593Smuzhiyun * for linking errors see 18*4882a593Smuzhiyun * http://lists.denx.de/pipermail/u-boot/2009-July/057350.html 19*4882a593Smuzhiyun */ 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #ifndef _CONFIG_KM_KIRKWOOD_H 22*4882a593Smuzhiyun #define _CONFIG_KM_KIRKWOOD_H 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* KM_KIRKWOOD */ 25*4882a593Smuzhiyun #if defined(CONFIG_KM_KIRKWOOD) 26*4882a593Smuzhiyun #define CONFIG_HOSTNAME km_kirkwood 27*4882a593Smuzhiyun #define CONFIG_KM_DISABLE_PCIE 28*4882a593Smuzhiyun #define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/ 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* KM_KIRKWOOD_PCI */ 31*4882a593Smuzhiyun #elif defined(CONFIG_KM_KIRKWOOD_PCI) 32*4882a593Smuzhiyun #define CONFIG_HOSTNAME km_kirkwood_pci 33*4882a593Smuzhiyun #define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/ 34*4882a593Smuzhiyun #define CONFIG_KM_FPGA_CONFIG 35*4882a593Smuzhiyun #define CONFIG_KM_UBI_PART_BOOT_OPTS ",2048" 36*4882a593Smuzhiyun #define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* KM_KIRKWOOD_128M16 */ 39*4882a593Smuzhiyun #elif defined(CONFIG_KM_KIRKWOOD_128M16) 40*4882a593Smuzhiyun #define CONFIG_HOSTNAME km_kirkwood_128m16 41*4882a593Smuzhiyun #undef CONFIG_SYS_KWD_CONFIG 42*4882a593Smuzhiyun #define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg 43*4882a593Smuzhiyun #define CONFIG_KM_DISABLE_PCIE 44*4882a593Smuzhiyun #define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/ 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* KM_NUSA / KM_SUGP1 */ 47*4882a593Smuzhiyun #elif defined(CONFIG_KM_NUSA) || defined(CONFIG_KM_SUGP1) 48*4882a593Smuzhiyun #define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/ 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun # if defined(CONFIG_KM_NUSA) 51*4882a593Smuzhiyun #define CONFIG_HOSTNAME kmnusa 52*4882a593Smuzhiyun # elif defined(CONFIG_KM_SUGP1) 53*4882a593Smuzhiyun #define CONFIG_HOSTNAME kmsugp1 54*4882a593Smuzhiyun #define KM_PCIE_RESET_MPP7 55*4882a593Smuzhiyun #endif 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #undef CONFIG_SYS_KWD_CONFIG 58*4882a593Smuzhiyun #define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg 59*4882a593Smuzhiyun #define CONFIG_KM_ENV_IS_IN_SPI_NOR 60*4882a593Smuzhiyun #define CONFIG_KM_FPGA_CONFIG 61*4882a593Smuzhiyun #define CONFIG_KM_PIGGY4_88E6352 62*4882a593Smuzhiyun #define CONFIG_MV88E6352_SWITCH 63*4882a593Smuzhiyun #define CONFIG_KM_MVEXTSW_ADDR 0x10 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun /* KM_MGCOGE3UN */ 66*4882a593Smuzhiyun #elif defined(CONFIG_KM_MGCOGE3UN) 67*4882a593Smuzhiyun #define CONFIG_HOSTNAME mgcoge3un 68*4882a593Smuzhiyun #define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/ 69*4882a593Smuzhiyun #undef CONFIG_SYS_KWD_CONFIG 70*4882a593Smuzhiyun #define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-memphis.cfg 71*4882a593Smuzhiyun #define CONFIG_KM_BOARD_EXTRA_ENV "waitforne=true\0" 72*4882a593Smuzhiyun #define CONFIG_PIGGY_MAC_ADRESS_OFFSET 3 73*4882a593Smuzhiyun #define CONFIG_KM_DISABLE_PCIE 74*4882a593Smuzhiyun #define CONFIG_KM_PIGGY4_88E6061 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun /* KMCOGE5UN */ 77*4882a593Smuzhiyun #elif defined(CONFIG_KM_COGE5UN) 78*4882a593Smuzhiyun #define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/ 79*4882a593Smuzhiyun #undef CONFIG_SYS_KWD_CONFIG 80*4882a593Smuzhiyun #define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_256M8_1.cfg 81*4882a593Smuzhiyun #define CONFIG_KM_ENV_IS_IN_SPI_NOR 82*4882a593Smuzhiyun #define CONFIG_PIGGY_MAC_ADRESS_OFFSET 3 83*4882a593Smuzhiyun #define CONFIG_HOSTNAME kmcoge5un 84*4882a593Smuzhiyun #define CONFIG_KM_DISABLE_PCIE 85*4882a593Smuzhiyun #define CONFIG_KM_PIGGY4_88E6352 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun /* KM_PORTL2 */ 88*4882a593Smuzhiyun #elif defined(CONFIG_KM_PORTL2) 89*4882a593Smuzhiyun #define CONFIG_HOSTNAME portl2 90*4882a593Smuzhiyun #define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/ 91*4882a593Smuzhiyun #define CONFIG_KM_PIGGY4_88E6061 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun /* KM_SUV31 */ 94*4882a593Smuzhiyun #elif defined(CONFIG_KM_SUV31) 95*4882a593Smuzhiyun #define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/ 96*4882a593Smuzhiyun #define CONFIG_HOSTNAME kmsuv31 97*4882a593Smuzhiyun #undef CONFIG_SYS_KWD_CONFIG 98*4882a593Smuzhiyun #define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg 99*4882a593Smuzhiyun #define CONFIG_KM_ENV_IS_IN_SPI_NOR 100*4882a593Smuzhiyun #define CONFIG_KM_FPGA_CONFIG 101*4882a593Smuzhiyun #define CONFIG_KM_UBI_PART_BOOT_OPTS ",2048" 102*4882a593Smuzhiyun #define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE 103*4882a593Smuzhiyun #else 104*4882a593Smuzhiyun #error ("Board unsupported") 105*4882a593Smuzhiyun #endif 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun /* include common defines/options for all arm based Keymile boards */ 108*4882a593Smuzhiyun #include "km/km_arm.h" 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun #if defined(CONFIG_KM_PIGGY4_88E6352) 111*4882a593Smuzhiyun /* 112*4882a593Smuzhiyun * Some keymile boards like mgcoge5un & nusa1 have their PIGGY4 connected via 113*4882a593Smuzhiyun * an Marvell 88E6352 simple switch. 114*4882a593Smuzhiyun * In this case we have to change the default settings for the etherent mac. 115*4882a593Smuzhiyun * There is NO ethernet phy. The ARM and Switch are conencted directly over 116*4882a593Smuzhiyun * RGMII in MAC-MAC mode 117*4882a593Smuzhiyun * In this case 1GBit full duplex and autoneg off 118*4882a593Smuzhiyun */ 119*4882a593Smuzhiyun #define PORT_SERIAL_CONTROL_VALUE ( \ 120*4882a593Smuzhiyun MVGBE_FORCE_LINK_PASS | \ 121*4882a593Smuzhiyun MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \ 122*4882a593Smuzhiyun MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \ 123*4882a593Smuzhiyun MVGBE_ADV_NO_FLOW_CTRL | \ 124*4882a593Smuzhiyun MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ 125*4882a593Smuzhiyun MVGBE_FORCE_BP_MODE_NO_JAM | \ 126*4882a593Smuzhiyun (1 << 9) /* Reserved bit has to be 1 */ | \ 127*4882a593Smuzhiyun MVGBE_DO_NOT_FORCE_LINK_FAIL | \ 128*4882a593Smuzhiyun MVGBE_DIS_AUTO_NEG_SPEED_GMII | \ 129*4882a593Smuzhiyun MVGBE_DTE_ADV_0 | \ 130*4882a593Smuzhiyun MVGBE_MIIPHY_MAC_MODE | \ 131*4882a593Smuzhiyun MVGBE_AUTO_NEG_NO_CHANGE | \ 132*4882a593Smuzhiyun MVGBE_MAX_RX_PACKET_1552BYTE | \ 133*4882a593Smuzhiyun MVGBE_CLR_EXT_LOOPBACK | \ 134*4882a593Smuzhiyun MVGBE_SET_FULL_DUPLEX_MODE | \ 135*4882a593Smuzhiyun MVGBE_EN_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX |\ 136*4882a593Smuzhiyun MVGBE_SET_GMII_SPEED_TO_1000 |\ 137*4882a593Smuzhiyun MVGBE_SET_MII_SPEED_TO_100) 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun #endif 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun #ifdef CONFIG_KM_PIGGY4_88E6061 142*4882a593Smuzhiyun /* 143*4882a593Smuzhiyun * Some keymile boards like mgcoge3un have their PIGGY4 connected via 144*4882a593Smuzhiyun * an Marvell 88E6061 simple switch. 145*4882a593Smuzhiyun * In this case we have to change the default settings for the 146*4882a593Smuzhiyun * ethernet phy connected to the kirkwood. 147*4882a593Smuzhiyun * In this case 100MB full duplex and autoneg off 148*4882a593Smuzhiyun */ 149*4882a593Smuzhiyun #define PORT_SERIAL_CONTROL_VALUE ( \ 150*4882a593Smuzhiyun MVGBE_FORCE_LINK_PASS | \ 151*4882a593Smuzhiyun MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \ 152*4882a593Smuzhiyun MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \ 153*4882a593Smuzhiyun MVGBE_ADV_NO_FLOW_CTRL | \ 154*4882a593Smuzhiyun MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ 155*4882a593Smuzhiyun MVGBE_FORCE_BP_MODE_NO_JAM | \ 156*4882a593Smuzhiyun (1 << 9) /* Reserved bit has to be 1 */ | \ 157*4882a593Smuzhiyun MVGBE_DO_NOT_FORCE_LINK_FAIL | \ 158*4882a593Smuzhiyun MVGBE_DIS_AUTO_NEG_SPEED_GMII | \ 159*4882a593Smuzhiyun MVGBE_DTE_ADV_0 | \ 160*4882a593Smuzhiyun MVGBE_MIIPHY_MAC_MODE | \ 161*4882a593Smuzhiyun MVGBE_AUTO_NEG_NO_CHANGE | \ 162*4882a593Smuzhiyun MVGBE_MAX_RX_PACKET_1552BYTE | \ 163*4882a593Smuzhiyun MVGBE_CLR_EXT_LOOPBACK | \ 164*4882a593Smuzhiyun MVGBE_SET_FULL_DUPLEX_MODE | \ 165*4882a593Smuzhiyun MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX |\ 166*4882a593Smuzhiyun MVGBE_SET_GMII_SPEED_TO_10_100 |\ 167*4882a593Smuzhiyun MVGBE_SET_MII_SPEED_TO_100) 168*4882a593Smuzhiyun #endif 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun #ifdef CONFIG_KM_DISABLE_PCI 171*4882a593Smuzhiyun #undef CONFIG_KIRKWOOD_PCIE_INIT 172*4882a593Smuzhiyun #endif 173*4882a593Smuzhiyun 174*4882a593Smuzhiyun #endif /* _CONFIG_KM_KIRKWOOD */ 175