1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2006 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * Dave Liu <daveliu@freescale.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2007 Logic Product Development, Inc. 6*4882a593Smuzhiyun * Peter Barada <peterb@logicpd.com> 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Copyright (C) 2007 MontaVista Software, Inc. 9*4882a593Smuzhiyun * Anton Vorontsov <avorontsov@ru.mvista.com> 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * (C) Copyright 2008 12*4882a593Smuzhiyun * Heiko Schocher, DENX Software Engineering, hs@denx.de. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * (C) Copyright 2010 15*4882a593Smuzhiyun * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com 16*4882a593Smuzhiyun * 17*4882a593Smuzhiyun * (C) Copyright 2010-2011 18*4882a593Smuzhiyun * Thomas Reufer, KEYMILE Ltd, thomas.reufer@keymile.com 19*4882a593Smuzhiyun * 20*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 21*4882a593Smuzhiyun */ 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #ifndef __CONFIG_KM8321_COMMON_H 24*4882a593Smuzhiyun #define __CONFIG_KM8321_COMMON_H 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* 27*4882a593Smuzhiyun * High Level Configuration Options 28*4882a593Smuzhiyun */ 29*4882a593Smuzhiyun #define CONFIG_QE /* Has QE */ 30*4882a593Smuzhiyun #define CONFIG_MPC832x /* MPC832x CPU specific */ 31*4882a593Smuzhiyun #define CONFIG_KM8321 /* Keymile PBEC8321 board specific */ 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define CONFIG_KM_DEF_ARCH "arch=ppc_8xx\0" 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* include common defines/options for all 83xx Keymile boards */ 36*4882a593Smuzhiyun #include "km83xx-common.h" 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* 39*4882a593Smuzhiyun * System IO Config 40*4882a593Smuzhiyun */ 41*4882a593Smuzhiyun #define CONFIG_SYS_SICRL SICRL_IRQ_CKS 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* 44*4882a593Smuzhiyun * Hardware Reset Configuration Word 45*4882a593Smuzhiyun */ 46*4882a593Smuzhiyun #define CONFIG_SYS_HRCW_LOW (\ 47*4882a593Smuzhiyun HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ 48*4882a593Smuzhiyun HRCWL_DDR_TO_SCB_CLK_2X1 | \ 49*4882a593Smuzhiyun HRCWL_CSB_TO_CLKIN_2X1 | \ 50*4882a593Smuzhiyun HRCWL_CORE_TO_CSB_2_5X1 | \ 51*4882a593Smuzhiyun HRCWL_CE_PLL_VCO_DIV_2 | \ 52*4882a593Smuzhiyun HRCWL_CE_TO_PLL_1X3) 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #define CONFIG_SYS_HRCW_HIGH (\ 55*4882a593Smuzhiyun HRCWH_PCI_AGENT | \ 56*4882a593Smuzhiyun HRCWH_PCI_ARBITER_DISABLE | \ 57*4882a593Smuzhiyun HRCWH_CORE_ENABLE | \ 58*4882a593Smuzhiyun HRCWH_FROM_0X00000100 | \ 59*4882a593Smuzhiyun HRCWH_BOOTSEQ_DISABLE | \ 60*4882a593Smuzhiyun HRCWH_SW_WATCHDOG_DISABLE | \ 61*4882a593Smuzhiyun HRCWH_ROM_LOC_LOCAL_16BIT | \ 62*4882a593Smuzhiyun HRCWH_BIG_ENDIAN | \ 63*4882a593Smuzhiyun HRCWH_LALE_NORMAL) 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #define CONFIG_SYS_DDRCDR (\ 66*4882a593Smuzhiyun DDRCDR_EN | \ 67*4882a593Smuzhiyun DDRCDR_PZ_MAXZ | \ 68*4882a593Smuzhiyun DDRCDR_NZ_MAXZ | \ 69*4882a593Smuzhiyun DDRCDR_M_ODR) 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun #define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f 72*4882a593Smuzhiyun #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ 73*4882a593Smuzhiyun SDRAM_CFG_32_BE | \ 74*4882a593Smuzhiyun SDRAM_CFG_SREN | \ 75*4882a593Smuzhiyun SDRAM_CFG_HSE) 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 78*4882a593Smuzhiyun #define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) 79*4882a593Smuzhiyun #define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ 80*4882a593Smuzhiyun (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ 83*4882a593Smuzhiyun CSCONFIG_ODT_WR_CFG | \ 84*4882a593Smuzhiyun CSCONFIG_ROW_BIT_13 | \ 85*4882a593Smuzhiyun CSCONFIG_COL_BIT_10) 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun #define CONFIG_SYS_DDR_MODE 0x47860242 88*4882a593Smuzhiyun #define CONFIG_SYS_DDR_MODE2 0x8080c000 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ 91*4882a593Smuzhiyun (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ 92*4882a593Smuzhiyun (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ 93*4882a593Smuzhiyun (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ 94*4882a593Smuzhiyun (0 << TIMING_CFG0_WWT_SHIFT) | \ 95*4882a593Smuzhiyun (0 << TIMING_CFG0_RRT_SHIFT) | \ 96*4882a593Smuzhiyun (0 << TIMING_CFG0_WRT_SHIFT) | \ 97*4882a593Smuzhiyun (0 << TIMING_CFG0_RWT_SHIFT)) 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ 100*4882a593Smuzhiyun (2 << TIMING_CFG1_WRTORD_SHIFT) | \ 101*4882a593Smuzhiyun (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ 102*4882a593Smuzhiyun (3 << TIMING_CFG1_WRREC_SHIFT) | \ 103*4882a593Smuzhiyun (7 << TIMING_CFG1_REFREC_SHIFT) | \ 104*4882a593Smuzhiyun (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ 105*4882a593Smuzhiyun (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ 106*4882a593Smuzhiyun (3 << TIMING_CFG1_PRETOACT_SHIFT)) 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ 109*4882a593Smuzhiyun (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ 110*4882a593Smuzhiyun (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ 111*4882a593Smuzhiyun (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ 112*4882a593Smuzhiyun (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ 113*4882a593Smuzhiyun (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ 114*4882a593Smuzhiyun (5 << TIMING_CFG2_CPO_SHIFT)) 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun #define CONFIG_SYS_DDR_TIMING_3 0x00000000 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun #define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 119*4882a593Smuzhiyun #define CONFIG_SYS_KMBEC_FPGA_SIZE 128 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun /* EEprom support */ 122*4882a593Smuzhiyun #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun /* 125*4882a593Smuzhiyun * Local Bus Configuration & Clock Setup 126*4882a593Smuzhiyun */ 127*4882a593Smuzhiyun #define CONFIG_SYS_LCRR_DBYP 0x80000000 128*4882a593Smuzhiyun #define CONFIG_SYS_LCRR_EADC 0x00010000 129*4882a593Smuzhiyun #define CONFIG_SYS_LCRR_CLKDIV 0x00000002 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun #define CONFIG_SYS_LBC_LBCR 0x00000000 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun /* 134*4882a593Smuzhiyun * MMU Setup 135*4882a593Smuzhiyun */ 136*4882a593Smuzhiyun #define CONFIG_SYS_IBAT7L (0) 137*4882a593Smuzhiyun #define CONFIG_SYS_IBAT7U (0) 138*4882a593Smuzhiyun #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L 139*4882a593Smuzhiyun #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun #endif /* __CONFIG_KM8321_COMMON_H */ 142