1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2012 3*4882a593Smuzhiyun * Linaro 4*4882a593Smuzhiyun * Linus Walleij <linus.walleij@linaro.org> 5*4882a593Smuzhiyun * Common ARM Integrator configuration settings 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0x01000000 11*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_START 0x100000 12*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_END 0x10000000 13*4882a593Smuzhiyun #define CONFIG_SYS_TIMERBASE 0x13000100 /* Timer1 */ 14*4882a593Smuzhiyun #define CONFIG_SYS_LOAD_ADDR 0x7fc0 /* default load address */ 15*4882a593Smuzhiyun #define CONFIG_SYS_LONGHELP 16*4882a593Smuzhiyun #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) /* Size of malloc() pool */ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* Serial port PL010/PL011 through the device model */ 19*4882a593Smuzhiyun #define CONFIG_PL01X_SERIAL 20*4882a593Smuzhiyun #define CONFIG_CONS_INDEX 0 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 23*4882a593Smuzhiyun #define CONFIG_SETUP_MEMORY_TAGS 24*4882a593Smuzhiyun #define CONFIG_MISC_INIT_R /* call misc_init_r during start up */ 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* 27*4882a593Smuzhiyun * There are various dependencies on the core module (CM) fitted 28*4882a593Smuzhiyun * Users should refer to their CM user guide 29*4882a593Smuzhiyun */ 30*4882a593Smuzhiyun #include "armcoremodule.h" 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* 33*4882a593Smuzhiyun * Initialize and remap the core module, use SPD to detect memory size 34*4882a593Smuzhiyun * If CONFIG_SKIP_LOWLEVEL_INIT is not defined & 35*4882a593Smuzhiyun * the core module has a CM_INIT register 36*4882a593Smuzhiyun * then the U-Boot initialisation code will 37*4882a593Smuzhiyun * e.g. ARM Boot Monitor or pre-loader is repeated once 38*4882a593Smuzhiyun * (to re-initialise any existing CM_INIT settings to safe values). 39*4882a593Smuzhiyun * 40*4882a593Smuzhiyun * This is usually not the desired behaviour since the platform 41*4882a593Smuzhiyun * will either reboot into the ARM monitor (or pre-loader) 42*4882a593Smuzhiyun * or continuously cycle thru it without U-Boot running, 43*4882a593Smuzhiyun * depending upon the setting of Integrator/CP switch S2-4. 44*4882a593Smuzhiyun * 45*4882a593Smuzhiyun * However it may be needed if Integrator/CP switch S2-1 46*4882a593Smuzhiyun * is set OFF to boot direct into U-Boot. 47*4882a593Smuzhiyun * In that case comment out the line below. 48*4882a593Smuzhiyun */ 49*4882a593Smuzhiyun #define CONFIG_CM_INIT 50*4882a593Smuzhiyun #define CONFIG_CM_REMAP 51*4882a593Smuzhiyun #define CONFIG_CM_SPD_DETECT 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* 54*4882a593Smuzhiyun * The ARM boot monitor initializes the board. 55*4882a593Smuzhiyun * However, the default U-Boot code also performs the initialization. 56*4882a593Smuzhiyun * If desired, this can be prevented by defining SKIP_LOWLEVEL_INIT 57*4882a593Smuzhiyun * - see documentation supplied with board for details of how to choose the 58*4882a593Smuzhiyun * image to run at reset/power up 59*4882a593Smuzhiyun * e.g. whether the ARM Boot Monitor runs before U-Boot 60*4882a593Smuzhiyun */ 61*4882a593Smuzhiyun /* #define CONFIG_SKIP_LOWLEVEL_INIT */ 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun /* 64*4882a593Smuzhiyun * The ARM boot monitor does not relocate U-Boot. 65*4882a593Smuzhiyun * However, the default U-Boot code performs the relocation check, 66*4882a593Smuzhiyun * and may relocate the code if the memory map is changed. 67*4882a593Smuzhiyun * If necessary this can be prevented by defining SKIP_RELOCATE_UBOOT 68*4882a593Smuzhiyun */ 69*4882a593Smuzhiyun /* #define SKIP_CONFIG_RELOCATE_UBOOT */ 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* 72*4882a593Smuzhiyun * Physical Memory Map 73*4882a593Smuzhiyun */ 74*4882a593Smuzhiyun #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ 75*4882a593Smuzhiyun #define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ 76*4882a593Smuzhiyun #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ 77*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 78*4882a593Smuzhiyun #define CONFIG_SYS_INIT_RAM_SIZE PHYS_SDRAM_1_SIZE 79*4882a593Smuzhiyun #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \ 80*4882a593Smuzhiyun CONFIG_SYS_INIT_RAM_SIZE - \ 81*4882a593Smuzhiyun GENERATED_GBL_DATA_SIZE) 82*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun /* 85*4882a593Smuzhiyun * FLASH and environment organization 86*4882a593Smuzhiyun * Top varies according to amount fitted 87*4882a593Smuzhiyun * Reserve top 4 blocks of flash 88*4882a593Smuzhiyun * - ARM Boot Monitor 89*4882a593Smuzhiyun * - Unused 90*4882a593Smuzhiyun * - SIB block 91*4882a593Smuzhiyun * - U-Boot environment 92*4882a593Smuzhiyun */ 93*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_CFI 1 94*4882a593Smuzhiyun #define CONFIG_FLASH_CFI_DRIVER 1 95*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_BASE 0x24000000 96*4882a593Smuzhiyun #define CONFIG_SYS_MAX_FLASH_BANKS 1 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun /* Timeout values in ticks */ 99*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Erase Timeout */ 100*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Write Timeout */ 101*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_PROTECTION /* The devices have real protection */ 102*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */ 103