1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2004 3*4882a593Smuzhiyun * Texas Instruments. 4*4882a593Smuzhiyun * Richard Woodruff <r-woodruff2@ti.com> 5*4882a593Smuzhiyun * Kshitij Gupta <kshitij@ti.com> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Configuration settings for the phyCORE-i.MX31 board. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifndef __CONFIG_H 13*4882a593Smuzhiyun #define __CONFIG_H 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #include <asm/arch/imx-regs.h> 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* High Level Configuration Options */ 18*4882a593Smuzhiyun #define CONFIG_MX31 /* This is a mx31 */ 19*4882a593Smuzhiyun #define CONFIG_MX31_CLK32 32000 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 22*4882a593Smuzhiyun #define CONFIG_SETUP_MEMORY_TAGS 23*4882a593Smuzhiyun #define CONFIG_INITRD_TAG 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* 26*4882a593Smuzhiyun * Size of malloc() pool 27*4882a593Smuzhiyun */ 28*4882a593Smuzhiyun #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 512 * 1024) 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* 31*4882a593Smuzhiyun * Hardware drivers 32*4882a593Smuzhiyun */ 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define CONFIG_SYS_I2C 35*4882a593Smuzhiyun #define CONFIG_SYS_I2C_MXC 36*4882a593Smuzhiyun #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 37*4882a593Smuzhiyun #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 38*4882a593Smuzhiyun #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 39*4882a593Smuzhiyun #define CONFIG_SYS_I2C_CLK_OFFSET I2C2_CLK_OFFSET 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #define CONFIG_MXC_UART 42*4882a593Smuzhiyun #define CONFIG_MXC_UART_BASE UART1_BASE 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* allow to overwrite serial and ethaddr */ 45*4882a593Smuzhiyun #define CONFIG_ENV_OVERWRITE 46*4882a593Smuzhiyun #define CONFIG_CONS_INDEX 1 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /*********************************************************** 49*4882a593Smuzhiyun * Command definition 50*4882a593Smuzhiyun ***********************************************************/ 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:128k(uboot)ro," \ 54*4882a593Smuzhiyun "1536k(kernel),-(root)" 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #define CONFIG_NETMASK 255.255.255.0 57*4882a593Smuzhiyun #define CONFIG_IPADDR 192.168.23.168 58*4882a593Smuzhiyun #define CONFIG_SERVERIP 192.168.23.2 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #define CONFIG_EXTRA_ENV_SETTINGS \ 61*4882a593Smuzhiyun "bootargs_base=setenv bootargs console=ttySMX0,115200\0" \ 62*4882a593Smuzhiyun "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \ 63*4882a593Smuzhiyun "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \ 64*4882a593Smuzhiyun "bootargs_flash=setenv bootargs $(bootargs) " \ 65*4882a593Smuzhiyun "root=/dev/mtdblock2 rootfstype=jffs2\0" \ 66*4882a593Smuzhiyun "bootargs_mtd=setenv bootargs $(bootargs) $(mtdparts)\0" \ 67*4882a593Smuzhiyun "bootcmd=run bootcmd_net\0" \ 68*4882a593Smuzhiyun "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs;" \ 69*4882a593Smuzhiyun "tftpboot 0x80000000 $(uimage);bootm\0" \ 70*4882a593Smuzhiyun "bootcmd_flash=run bootargs_base bootargs_mtd bootargs_flash;" \ 71*4882a593Smuzhiyun "bootm 0x80000000\0" \ 72*4882a593Smuzhiyun "unlock=yes\0" \ 73*4882a593Smuzhiyun "mtdparts=" MTDPARTS_DEFAULT "\0" \ 74*4882a593Smuzhiyun "prg_uboot=tftpboot 0x80000000 $(uboot);" \ 75*4882a593Smuzhiyun "protect off 0xa0000000 +0x20000;" \ 76*4882a593Smuzhiyun "erase 0xa0000000 +0x20000;" \ 77*4882a593Smuzhiyun "cp.b 0x80000000 0xa0000000 $(filesize)\0" \ 78*4882a593Smuzhiyun "prg_kernel=tftpboot 0x80000000 $(uimage);" \ 79*4882a593Smuzhiyun "erase 0xa0040000 +0x180000;" \ 80*4882a593Smuzhiyun "cp.b 0x80000000 0xa0040000 $(filesize)\0" \ 81*4882a593Smuzhiyun "prg_jffs2=tftpboot 0x80000000 $(jffs2);" \ 82*4882a593Smuzhiyun "erase 0xa01c0000 0xa1ffffff;" \ 83*4882a593Smuzhiyun "cp.b 0x80000000 0xa01c0000 $(filesize)\0" \ 84*4882a593Smuzhiyun "videomode=video=ctfb:x:240,y:320,depth:16,mode:0," \ 85*4882a593Smuzhiyun "pclk:185925,le:9,ri:17,up:7,lo:10,hs:1,vs:1," \ 86*4882a593Smuzhiyun "sync:1241513985,vmode:0\0" 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun #define CONFIG_SMC911X 89*4882a593Smuzhiyun #define CONFIG_SMC911X_BASE 0xa8000000 90*4882a593Smuzhiyun #define CONFIG_SMC911X_32_BIT 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun /* 93*4882a593Smuzhiyun * Miscellaneous configurable options 94*4882a593Smuzhiyun */ 95*4882a593Smuzhiyun #define CONFIG_SYS_LONGHELP /* undef to save memory */ 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ 98*4882a593Smuzhiyun #define CONFIG_SYS_MEMTEST_END 0x10000 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun #define CONFIG_SYS_LOAD_ADDR 0 /* default load address */ 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun #define CONFIG_CMDLINE_EDITING 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun /* 105*4882a593Smuzhiyun * Physical Memory Map 106*4882a593Smuzhiyun */ 107*4882a593Smuzhiyun #define CONFIG_NR_DRAM_BANKS 1 108*4882a593Smuzhiyun #define PHYS_SDRAM_1 0x80000000 109*4882a593Smuzhiyun #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) 110*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0xA0000000 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 113*4882a593Smuzhiyun #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 114*4882a593Smuzhiyun #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 115*4882a593Smuzhiyun #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 116*4882a593Smuzhiyun GENERATED_GBL_DATA_SIZE) 117*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 118*4882a593Smuzhiyun CONFIG_SYS_GBL_DATA_OFFSET) 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun /* 121*4882a593Smuzhiyun * FLASH and environment organization 122*4882a593Smuzhiyun */ 123*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_BASE 0xa0000000 124*4882a593Smuzhiyun #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max # of memory banks */ 125*4882a593Smuzhiyun #define CONFIG_SYS_MAX_FLASH_SECT 259 /* max # of sectors/chip */ 126*4882a593Smuzhiyun /* Monitor at beginning of flash */ 127*4882a593Smuzhiyun #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun #define CONFIG_ENV_OFFSET 0x00 /* env. starts here */ 130*4882a593Smuzhiyun #define CONFIG_ENV_SIZE 4096 131*4882a593Smuzhiyun #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 132*4882a593Smuzhiyun #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 5 bits = 32 octets */ 133*4882a593Smuzhiyun #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* 10 ms delay */ 134*4882a593Smuzhiyun #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* byte addr. lenght */ 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun /* 137*4882a593Smuzhiyun * CFI FLASH driver setup 138*4882a593Smuzhiyun */ 139*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */ 140*4882a593Smuzhiyun #define CONFIG_FLASH_CFI_DRIVER /* Use drivers/mtd/cfi_flash.c */ 141*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffered writes (~10x faster) */ 142*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_PROTECTION /* Use hardware sector protection */ 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun /* 145*4882a593Smuzhiyun * Timeout for Flash Erase and Flash Write 146*4882a593Smuzhiyun * timeout values are in ticks 147*4882a593Smuzhiyun */ 148*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_ERASE_TOUT (100*CONFIG_SYS_HZ) 149*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_WRITE_TOUT (100*CONFIG_SYS_HZ) 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun /* 152*4882a593Smuzhiyun * JFFS2 partitions 153*4882a593Smuzhiyun */ 154*4882a593Smuzhiyun #define CONFIG_JFFS2_DEV "nor0" 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun /* EET platform additions */ 157*4882a593Smuzhiyun #ifdef CONFIG_TARGET_IMX31_PHYCORE_EET 158*4882a593Smuzhiyun #define CONFIG_MXC_GPIO 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun #define CONFIG_HARD_SPI 161*4882a593Smuzhiyun #define CONFIG_MXC_SPI 162*4882a593Smuzhiyun 163*4882a593Smuzhiyun #define CONFIG_S6E63D6 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun #define CONFIG_VIDEO_MX3 166*4882a593Smuzhiyun #define CONFIG_VIDEO_LOGO 167*4882a593Smuzhiyun #define CONFIG_SPLASH_SCREEN 168*4882a593Smuzhiyun #define CONFIG_BMP_16BPP 169*4882a593Smuzhiyun #endif 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun #endif /* __CONFIG_H */ 172