1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * iPAQ h2200 board configuration 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2012 Lukasz Dalek <luk0104@gmail.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __CONFIG_H 10*4882a593Smuzhiyun #define __CONFIG_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define CONFIG_MACH_TYPE MACH_TYPE_H2200 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define CONFIG_CPU_PXA25X 1 15*4882a593Smuzhiyun #define CONFIG_BOARD_H2200 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define CONFIG_NR_DRAM_BANKS 1 18*4882a593Smuzhiyun #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ 19*4882a593Smuzhiyun #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 22*4882a593Smuzhiyun #define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_1_SIZE 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_ADDR 0xfffff800 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define CONFIG_ENV_SIZE 0x00040000 27*4882a593Smuzhiyun #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define CONFIG_SYS_LOAD_ADDR 0xa3000000 /* default load address */ 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* 32*4882a593Smuzhiyun * iPAQ 1st stage bootloader loads 2nd stage bootloader 33*4882a593Smuzhiyun * at address 0xa0040000 but bootloader requires header 34*4882a593Smuzhiyun * which is 0x1000 long. 35*4882a593Smuzhiyun * 36*4882a593Smuzhiyun * --- Header begin --- 37*4882a593Smuzhiyun * .word 0xea0003fe ; b 0x1000 38*4882a593Smuzhiyun * 39*4882a593Smuzhiyun * .org 0x40 40*4882a593Smuzhiyun * .ascii "ECEC" 41*4882a593Smuzhiyun * 42*4882a593Smuzhiyun * .org 0x1000 43*4882a593Smuzhiyun * --- Header end --- 44*4882a593Smuzhiyun */ 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0xa0041000 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* 49*4882a593Smuzhiyun * Static chips 50*4882a593Smuzhiyun */ 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define CONFIG_SYS_MSC0_VAL 0x246c7ffc 53*4882a593Smuzhiyun #define CONFIG_SYS_MSC1_VAL 0x7ff07ff0 54*4882a593Smuzhiyun #define CONFIG_SYS_MSC2_VAL 0x7ff07ff0 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* 57*4882a593Smuzhiyun * PCMCIA and CF Interfaces 58*4882a593Smuzhiyun */ 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #define CONFIG_SYS_MECR_VAL 0x00000000 61*4882a593Smuzhiyun #define CONFIG_SYS_MCMEM0_VAL 0x00000000 62*4882a593Smuzhiyun #define CONFIG_SYS_MCMEM1_VAL 0x00000000 63*4882a593Smuzhiyun #define CONFIG_SYS_MCATT0_VAL 0x00000000 64*4882a593Smuzhiyun #define CONFIG_SYS_MCATT1_VAL 0x00000000 65*4882a593Smuzhiyun #define CONFIG_SYS_MCIO0_VAL 0x00000000 66*4882a593Smuzhiyun #define CONFIG_SYS_MCIO1_VAL 0x00000000 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun #define CONFIG_SYS_FLYCNFG_VAL 0x00000000 69*4882a593Smuzhiyun #define CONFIG_SYS_SXCNFG_VAL 0x00040004 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun #define CONFIG_SYS_MDREFR_VAL 0x0099E018 72*4882a593Smuzhiyun #define CONFIG_SYS_MDCNFG_VAL 0x01C801CB 73*4882a593Smuzhiyun #define CONFIG_SYS_MDMRS_VAL 0x00220022 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun #define CONFIG_SYS_PSSR_VAL 0x00000000 76*4882a593Smuzhiyun #define CONFIG_SYS_CKEN 0x00004840 77*4882a593Smuzhiyun #define CONFIG_SYS_CCCR 0x00000161 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun /* 80*4882a593Smuzhiyun * GPIOs 81*4882a593Smuzhiyun */ 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun #define CONFIG_SYS_GPSR0_VAL 0x01000000 84*4882a593Smuzhiyun #define CONFIG_SYS_GPSR1_VAL 0x00000000 85*4882a593Smuzhiyun #define CONFIG_SYS_GPSR2_VAL 0x00010000 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun #define CONFIG_SYS_GPCR0_VAL 0x00000000 88*4882a593Smuzhiyun #define CONFIG_SYS_GPCR1_VAL 0x00000000 89*4882a593Smuzhiyun #define CONFIG_SYS_GPCR2_VAL 0x00000000 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun #define CONFIG_SYS_GPDR0_VAL 0xF7E38C00 92*4882a593Smuzhiyun #define CONFIG_SYS_GPDR1_VAL 0xBCFFBF83 93*4882a593Smuzhiyun #define CONFIG_SYS_GPDR2_VAL 0x000157FF 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun #define CONFIG_SYS_GAFR0_L_VAL 0x80401000 96*4882a593Smuzhiyun #define CONFIG_SYS_GAFR0_U_VAL 0x00000112 97*4882a593Smuzhiyun #define CONFIG_SYS_GAFR1_L_VAL 0x600A9550 98*4882a593Smuzhiyun #define CONFIG_SYS_GAFR1_U_VAL 0x0005AAAA 99*4882a593Smuzhiyun #define CONFIG_SYS_GAFR2_L_VAL 0x20000000 100*4882a593Smuzhiyun #define CONFIG_SYS_GAFR2_U_VAL 0x00000000 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun /* 103*4882a593Smuzhiyun * Serial port 104*4882a593Smuzhiyun */ 105*4882a593Smuzhiyun #define CONFIG_FFUART 106*4882a593Smuzhiyun #define CONFIG_CONS_INDEX 3 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 38400, 115200 } 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun #define CONFIG_SETUP_MEMORY_TAGS 111*4882a593Smuzhiyun #define CONFIG_CMDLINE_TAG 112*4882a593Smuzhiyun #define CONFIG_INITRD_TAG 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun /* Monitor Command Prompt */ 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun #define CONFIG_USB_DEV_PULLUP_GPIO 33 117*4882a593Smuzhiyun /* USB VBUS GPIO 3 */ 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun #define CONFIG_BOOTCOMMAND \ 120*4882a593Smuzhiyun "setenv downloaded 0 ; while test $downloaded -eq 0 ; do " \ 121*4882a593Smuzhiyun "if bootp ; then setenv downloaded 1 ; fi ; done ; " \ 122*4882a593Smuzhiyun "source :script ; " \ 123*4882a593Smuzhiyun "bootm ; " 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun #define CONFIG_USB_GADGET_PXA2XX 126*4882a593Smuzhiyun #define CONFIG_USB_ETH_SUBSET 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun #define CONFIG_USBNET_DEV_ADDR "de:ad:be:ef:00:01" 129*4882a593Smuzhiyun #define CONFIG_EXTRA_ENV_SETTINGS \ 130*4882a593Smuzhiyun "stdin=serial\0" \ 131*4882a593Smuzhiyun "stdout=serial\0" \ 132*4882a593Smuzhiyun "stderr=serial\0" 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun #endif /* __CONFIG_H */ 135