1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * include/configs/gose.h 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2014 Renesas Electronics Corporation 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __GOSE_H 10*4882a593Smuzhiyun #define __GOSE_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #undef DEBUG 13*4882a593Smuzhiyun #define CONFIG_R8A7793 14*4882a593Smuzhiyun #define CONFIG_ARCH_RMOBILE_BOARD_STRING "Gose" 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #include "rcar-gen2-common.h" 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT) 19*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0x70000000 20*4882a593Smuzhiyun #else 21*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0xE6304000 22*4882a593Smuzhiyun #endif 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* STACK */ 25*4882a593Smuzhiyun #if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT) 26*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC 27*4882a593Smuzhiyun #else 28*4882a593Smuzhiyun #define CONFIG_SYS_INIT_SP_ADDR 0xE633FFFC 29*4882a593Smuzhiyun #endif 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define STACK_AREA_SIZE 0xC000 32*4882a593Smuzhiyun #define LOW_LEVEL_MERAM_STACK \ 33*4882a593Smuzhiyun (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* MEMORY */ 36*4882a593Smuzhiyun #define RCAR_GEN2_SDRAM_BASE 0x40000000 37*4882a593Smuzhiyun #define RCAR_GEN2_SDRAM_SIZE 0x40000000 38*4882a593Smuzhiyun #define RCAR_GEN2_UBOOT_SDRAM_SIZE 0x20000000 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* SH Ether */ 41*4882a593Smuzhiyun #define CONFIG_SH_ETHER 42*4882a593Smuzhiyun #define CONFIG_SH_ETHER_USE_PORT 0 43*4882a593Smuzhiyun #define CONFIG_SH_ETHER_PHY_ADDR 0x1 44*4882a593Smuzhiyun #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII 45*4882a593Smuzhiyun #define CONFIG_SH_ETHER_CACHE_WRITEBACK 46*4882a593Smuzhiyun #define CONFIG_SH_ETHER_CACHE_INVALIDATE 47*4882a593Smuzhiyun #define CONFIG_BITBANGMII 48*4882a593Smuzhiyun #define CONFIG_BITBANGMII_MULTI 49*4882a593Smuzhiyun #define CONFIG_SH_ETHER_ALIGNE_SIZE 64 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* Board Clock */ 52*4882a593Smuzhiyun #define RMOBILE_XTAL_CLK 20000000u 53*4882a593Smuzhiyun #define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK 54*4882a593Smuzhiyun #define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) 55*4882a593Smuzhiyun #define CONFIG_SYS_TMU_CLK_DIV 4 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /* I2C */ 58*4882a593Smuzhiyun #define CONFIG_SYS_I2C 59*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SH 60*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SLAVE 0x7F 61*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3 62*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SH_SPEED0 400000 63*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SH_SPEED1 400000 64*4882a593Smuzhiyun #define CONFIG_SYS_I2C_SH_SPEED2 400000 65*4882a593Smuzhiyun #define CONFIG_SH_I2C_DATA_HIGH 4 66*4882a593Smuzhiyun #define CONFIG_SH_I2C_DATA_LOW 5 67*4882a593Smuzhiyun #define CONFIG_SH_I2C_CLOCK 10000000 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */ 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* USB */ 72*4882a593Smuzhiyun #define CONFIG_USB_EHCI_RMOBILE 73*4882a593Smuzhiyun #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun /* Module stop status bits */ 76*4882a593Smuzhiyun /* INTC-RT */ 77*4882a593Smuzhiyun #define CONFIG_SMSTP0_ENA 0x00400000 78*4882a593Smuzhiyun /* MSIF */ 79*4882a593Smuzhiyun #define CONFIG_SMSTP2_ENA 0x00002000 80*4882a593Smuzhiyun /* INTC-SYS, IRQC */ 81*4882a593Smuzhiyun #define CONFIG_SMSTP4_ENA 0x00000180 82*4882a593Smuzhiyun /* SCIF0 */ 83*4882a593Smuzhiyun #define CONFIG_SMSTP7_ENA 0x00200000 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun /* SDHI */ 86*4882a593Smuzhiyun #define CONFIG_SH_SDHI_FREQ 97500000 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun #endif /* __GOSE_H */ 89