1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Configuration settings for the Espresso7420 board. 3*4882a593Smuzhiyun * Copyright (C) 2016 Samsung Electronics 4*4882a593Smuzhiyun * Thomas Abraham <thomas.ab@samsung.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __CONFIG_EXYNOS7420_COMMON_H 10*4882a593Smuzhiyun #define __CONFIG_EXYNOS7420_COMMON_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* High Level Configuration Options */ 13*4882a593Smuzhiyun #define CONFIG_SAMSUNG /* in a SAMSUNG core */ 14*4882a593Smuzhiyun #define CONFIG_EXYNOS7420 /* Exynos7 Family */ 15*4882a593Smuzhiyun #define CONFIG_S5P 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #include <asm/arch/cpu.h> /* get chip and board defs */ 18*4882a593Smuzhiyun #include <linux/sizes.h> 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define CONFIG_ARCH_CPU_INIT 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* Size of malloc() pool before and after relocation */ 23*4882a593Smuzhiyun #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 << 20)) 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* Miscellaneous configurable options */ 26*4882a593Smuzhiyun #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 27*4882a593Smuzhiyun #define CONFIG_SYS_PBSIZE 1024 /* Print Buffer Size */ 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* Boot Argument Buffer Size */ 30*4882a593Smuzhiyun #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* select serial console configuration */ 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* Timer input clock frequency */ 35*4882a593Smuzhiyun #define COUNTER_FREQUENCY 24000000 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* Device Tree */ 38*4882a593Smuzhiyun #define CONFIG_DEVICE_TREE_LIST "exynos7420-espresso7420" 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* IRAM Layout */ 41*4882a593Smuzhiyun #define CONFIG_IRAM_BASE 0x02100000 42*4882a593Smuzhiyun #define CONFIG_IRAM_SIZE 0x58000 43*4882a593Smuzhiyun #define CONFIG_IRAM_END (CONFIG_IRAM_BASE + CONFIG_IRAM_SIZE) 44*4882a593Smuzhiyun #define CPU_RELEASE_ADDR secondary_boot_addr 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* Number of CPUs available */ 47*4882a593Smuzhiyun #define CONFIG_CORE_COUNT 0x8 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* select serial console configuration */ 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE 54*4882a593Smuzhiyun #define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE 55*4882a593Smuzhiyun #define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) 56*4882a593Smuzhiyun #define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE 57*4882a593Smuzhiyun #define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) 58*4882a593Smuzhiyun #define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE 59*4882a593Smuzhiyun #define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) 60*4882a593Smuzhiyun #define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE 61*4882a593Smuzhiyun #define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE)) 62*4882a593Smuzhiyun #define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE 63*4882a593Smuzhiyun #define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE)) 64*4882a593Smuzhiyun #define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE 65*4882a593Smuzhiyun #define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE)) 66*4882a593Smuzhiyun #define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE 67*4882a593Smuzhiyun #define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE)) 68*4882a593Smuzhiyun #define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun /* Configuration of ENV Blocks */ 71*4882a593Smuzhiyun #define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */ 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #define BOOT_TARGET_DEVICES(func) \ 74*4882a593Smuzhiyun func(MMC, mmc, 1) \ 75*4882a593Smuzhiyun func(MMC, mmc, 0) \ 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun #ifndef MEM_LAYOUT_ENV_SETTINGS 78*4882a593Smuzhiyun #define MEM_LAYOUT_ENV_SETTINGS \ 79*4882a593Smuzhiyun "bootm_size=0x10000000\0" \ 80*4882a593Smuzhiyun "kernel_addr_r=0x42000000\0" \ 81*4882a593Smuzhiyun "fdt_addr_r=0x43000000\0" \ 82*4882a593Smuzhiyun "ramdisk_addr_r=0x43300000\0" \ 83*4882a593Smuzhiyun "scriptaddr=0x50000000\0" \ 84*4882a593Smuzhiyun "pxefile_addr_r=0x51000000\0" 85*4882a593Smuzhiyun #endif 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun #ifndef EXYNOS_DEVICE_SETTINGS 88*4882a593Smuzhiyun #define EXYNOS_DEVICE_SETTINGS \ 89*4882a593Smuzhiyun "stdin=serial\0" \ 90*4882a593Smuzhiyun "stdout=serial\0" \ 91*4882a593Smuzhiyun "stderr=serial\0" 92*4882a593Smuzhiyun #endif 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun #ifndef EXYNOS_FDTFILE_SETTING 95*4882a593Smuzhiyun #define EXYNOS_FDTFILE_SETTING 96*4882a593Smuzhiyun #endif 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun #define CONFIG_EXTRA_ENV_SETTINGS \ 99*4882a593Smuzhiyun EXYNOS_DEVICE_SETTINGS \ 100*4882a593Smuzhiyun EXYNOS_FDTFILE_SETTING \ 101*4882a593Smuzhiyun MEM_LAYOUT_ENV_SETTINGS 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun #endif /* __CONFIG_EXYNOS7420_COMMON_H */ 104